8

Preface: Speculations of an alternate history are unfit for RC.SE, so this answer is restricted to fact checking. TL;DR; From a software (Kernal) PoV there is no reason for using a 6526, but there are two indicators from the hurried design case and business case: Volume. The new 652x family member (*1) was designated to be the base I/O chip for all upcoming ...


8

Klaus Dorman's functional tests for the 6502 are fantastic: https://github.com/Klaus2m5/6502_65C02_functional_tests


7

No external pull-up is needed as the CIA already got internal circuitry to do so. Port A and B have passive pull-up devices as well as active pull-ups Taken from the CSG 6526 data sheet, section "I/O Ports" on page 5.


3

I am unaware of any formalised test suite for either the 6520 or 6522. The 6526 is at least partially covered by Wolfgang Lorenz's C64 test suite. Because of the applicability to other machines, you usually see it documented for its 6502 tests (and the outward link to the suite itself there is broken; instead try that listed here) but it includes a ...


2

[This is an attempt to summarize my understanding of the other answers. Feel free to correct this or complain if you think this restatement isn't useful.] The misunderstanding by the OP (me) is that because a specific design (the C64 keyboard/joystick interface) uses this chip in a certain way, using it that way was the intent of the design. The primary ...


2

the PA0-7 and PB0-7 pins: always act as inputs, even when the data direction register (DDR) is set to 1 ("output") for that pin, Correct. the outputs are open drain, so setting 1 in both the DDR and the Peripheral Data Register (PR) has the same effect as setting 0 in the DDR and any value in the PR. Not quite. The datasheet says:- ...


1

This is a very common configuration for general purpose I/O pins. Output Mode The DDR register switches the output drivers on and off. When a pin's bit is set to 1, the pin drives either high or low, controlled by the PR register. It can source of sink current. The datasheet says minimum 200uA source, 3.2mA sink, on page 3. So shorting to GND when the ...


1

1) If the DDR sets pin as output, the output data pin is a TTL push pull output and otherwise it is a TTL input with pull-up. Reading the data register does give the actual state of the pin, no matter if it is input or output. But as we are talking about TTL outputs, they are extremely weak at sourcing current. As per the datasheet, output high current is ...


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