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35

They both shared the same memory so it didn't really forward instructions. The Z80 card stopped the 6502 running using the DMA signals and the system swapped between the two by writing to $CN00 where N is the slot number. Since the memory was shared the Z80 stuffed some values (A,X,Y,P) into the 6502 zero page ($F045 and up from the Z80 side) stored the ...


29

No, there is no simple one-to-one mapping for the pins. (Bolded signal names will be active-low.) For example, while the 286 has two physical pins for interrupts (INTR and NMI), 68000 has three (IPL0, IPL1 and IPL2), encoding a total of 7 interrupt levels. So the interrupts are handled differently, and also the signaling for acknowledging an interrupt at ...


29

The MOVE immediate instruction takes 8 cycles in byte and word modes. There are two memory reads, one for the instruction and one for the immediate value. The MOVEQ instruction encodes the immediate value into the instruction op-code itself, so only takes 4 cycles and 1 memory read. It can only take a byte immediate value. MOVEQ #1, D0 (4 clocks, 1 ...


25

Yes, IBM System z mainframes (and their predecessors) have been using "mainframe-on-a-chip" microprocessors for a couple decades now. In 1995 I used a IBM PS/2 with an IBM System/390 Processor Card in it running MVS. It executed System/390 instructions natively, using (I believe) one of the same microprocessors used in the System/390 mainframes of the time. ...


24

If you look at the datasheet of a typical DRAM chip of this era, say the Mostek 4116, it indeed has a cycle time of 375ns, so you can't access it at more than 2.6 MHz. But don't confuse the clock rate of a microprocessor with the bus timing. Looking at figure 4-1 of the 68000 datasheet, a simple byte read or write bus cycle take 8 CPU cycles, and the simple ...


20

The (plain) 68k never had anything directly comparable to the Intel x86 range's Protected Mode. When Intel introduced the Protected mode (PM) to its x86 range of CPUs, this lifted a number of restrictions, though, that the 68k range never had: PM allowed the OS designer to protect (hence the name...) certain address ranges from access from non-privileged ...


20

All of the 68k-based computers (Amiga, Atari ST and Sinclair QL, as well as the classic Macintosh) went to market in a rush. And all of them went to market before the OS (and, thus, the ROMs) were really "finished". The QL initially had an outboard ROM extension that later on had to be replaced with the "final" ROMs (so, the computer had to be sent back to ...


16

Most obvious question first: why not puting itn on a ISA Card and take over the bus instead? Given, there would be still some work to be done after asking for DMA and pulling /MASTER, but way less than emulating a totally different CPU protocoll. More like adapting to a weired memory subsystem. But for your points First, most obviously, they are ...


15

It was part of the 68000 system architecture in which all the interrupt vectors are low in the memory map. The first 1024 bytes are reserved for these vectors and if a program / os need to change these, hardcoding into ROM wouldn't work. The vendor (Motorola) had application notes in which on a cold boot or reset, the ROM was mapped low. The idea came ...


14

The Zilog Z8000, Motorola 68000, and Intel 8086 all arrived at roughly the same time-frame and each represented the new 16-bit architecture of their respective CPU designers. They differed markedly in their approach to hardware memory addressing. The Z8000 and the 8086 used a segmented memory approach, whereas the 68000 was a flat address space, and focused ...


14

Did Nintendo really change their mind about using the 68000? Hard to say, as these decisions were never public. If so, how does this square with that CPU being so cheap even two years before the launch of the new console? Maybe because the price of the CPU drops to almost zero when using the 65816 as IP. After all, they didn't use the stock CPU, but had ...


14

I can suggest why it was created. The Wikipedia page for CPU32 says: The instruction set of the CPU32 core is similar to the 68020 without bitfield instructions, and with a few instructions unique to the CPU32 core, such as table lookup and interpolate instructions, and a low-power stop mode. The objective for CPU32 seems to have been a processor for ...


13

The main benefit for learning computer system architecture with a retrocomputer, compared to a modern computer, is accessibility of the hardware. Retrocomputers are much simpler than modern systems in terms of both the hardware and the system software. By design and necessity, programming on a retrocomputer means often programming the bare metal, and that ...


12

TL;DR: this longish answer address the "mystic" property of the question; i.e., the sense of wonder about how this could be possible; not the actual workings of the specific components. The gory details have been given in other answers, but here is a broader outlook on the issue: Remember that in that time, computers (certainly home computers) were, ...


11

To give the exact cycle-by-cycle breakdown: MOVEQ is a one word instruction so will nominally perform in four cycles; in practice it can occur immediately following operation decoding because all necessary information is within the instruction word. Four cycles are then expended fetching the next value to feed into the instruction prefetch queue. Both MOVE....


10

AllocEntry() sets bit 31 of the address to signal failure, so cannot indicate success for addresses beyond the 2GiB boundary. This limits AmigaOS to slightly less than 2GiB of general-purpose RAM due to ROM and I/O also sharing the space. Zorro III cards can (and do) use address space beyond 2GiB, even for RAM such as a frame buffer, so long as it's not ...


10

I'm curious what burst mode was on the 68030 and It's an extension to the 68020 bus protocol offered by the 68030. By default, all read access on a 68k takes two cycles. Cache Burst uses the same two-cycle synchronous access for the first word but reduces any of the three subsequent accesses to a single cycle, thus reducing the time for a cache line of 4 ...


10

Based on the absolute dearth of information on the Motorola 68486/68487 video chipset (RMS), I would conclude that it was never officially released as a product for OEMs, and was therefore never used in any actual computer products. [UPDATE: Per OP finding, it appears that one company, Micro Concepts of the UK, was offering an SBC based on the 68000/010 ...


9

An internal access fault also occurs when the data or instruction MMU detects that a successful address translation is not possible because the page is write protected, supervisor only, or nonresident. (My emphasis.) So, one major case of an internal access fault is an MMU detected condition, where the page is not resident, i.e. a page fault. ...


8

Actually, it's 256 MB only for A4000/T CPU cards - it's 128 MB for A3000/T cards. The reason for this is that Fat Gary asserts the _RAMSLOT signal for this memory window. That way, the CPU card knows when to activate the RAM controller and to run an internal cycle. Overcoming this limit is (probably) possible but would require a complete address decoder ...


7

Chip collectors I know are generally looking for a few things: Early production dates — chips often have a date code of the form YYWW (eg 8651 for the 51st week of 1986). The earliest ones have more value to collectors. Unusual technologies — if a chip used a short-lived or esoteric technology, it's generally considered more ‘interesting’. Non-standard ...


7

The 4 clock cycles per memory access was for instruction fetch and the 68000 could actually take longer. (Internal Architecture of 68000 was 3 16-bit Arithmetic Logic Units; 2 for Data registers and 1 for Address meaning that 32-bit addresses took longer to calculate. This was from IBM XT/370 info that used a 68000 microprogrammed to execute IBM mainframe ...


7

68000 had a protected mode as well (i.e. a special mode allowing the use of privileged/supervisor instructions not normally available to user code). Err, no. At least don't call it protected mode, call it supervisor mode or privileged mode. "Protected mode" implies something like the >=80286 protected mode which had hardware memory protection. This did not ...


7

So far as I recall, the Macintosh System Software didn't bother with the user versus supervisor mode distinction. Even after the release of System 7, which supported virtual memory, virtually everything ran in supervisor mode. I think the Apple Lisa, which had a more minicomputer-like (or what we'd today call Unix-like) operating system design, as well as ...


7

I've searched the manual and cannot find why it's "quick". Simply because MOVEQ is a single word (two byte) instruction, which can be fetched in a single memory cycle, while an equal constant move will be 2 (MOVE.W) or 3 words (MOVE.L) and need one/two additional memory cycles - each four clocks. So effectively you'll get the following execution timing: ...


6

I would say the answer to the question is no.There are two reasons for this. Firstly, a retro computer is still a box with a circuit board in it and some chips soldered to it. Actually looking at its insides isn't going to leave you any more the wiser than looking at the insides of a modern desktop PC. Secondly retro computers - well, 1970s and 80s era ...


6

I'm not sure if a general MACSbug was ever available. AFAIR Motorola did supply it only to OEM. They even had a special manual for OEM manufacturers regarding the adaption of MACSbug I/O functions and adding new commands (like Apple did for ES (Exit to Shell) and RB (ReBoot)). Many of them gave the resulting product a name of their choice. Then again, being ...


6

I was at college 1979-83, studying computing, and remember being told in a microprocessor course that the Z8000 wasn't very good. After a browse through the user's manual I can see why. The memory model seems to have been designed by a hardware engineer who didn't think very much about software. Indeed, the whole architecture seems designed to do the same ...


6

I'm trying to understand the difference in bus cycles, A bus sycle is one transaction on the processor bus. Roughly one read or write. clock cycles A clock cycle is one high and low phase of the clock signal ... well, a cycle. and states within a 68000 processor. States are the in general the steps the CPU takes to execute an instruction - here ...


6

Chips aren't either "RISC" or "CISC"; they fall on a spectrum between the two. The 68000 is less "CISC" than an 80x86, for example, and you could plausibly call the 6502 a somewhat "RISC" processor by the kind of definitions used that make the Amtel AVR "RISC." This isn't really very useful as a guideline for how much processing power you have. And MIPS ...


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