37

The basic principle behind overclocking is that if you speed up a clock, everything that runs from that clock will go faster. But there are some parts of your computer that you don't want to speed up, and NTSC (or PAL) video output is one of them. In order for C64 output to be displayed correctly on an NTSC/PAL monitor, it needs to be sent to the monitor ...


32

Worshipping at the altar of color clock Back in that day, everything was built around the NTSC color clock frequency of 3.579545 MHz. Everything from the Atari VCS to the C64 made ample use of it, because some iteration of your product would inevitably need to talk to a commodity color NTSC display operating at that frequency. This will come up; so FYI ...


26

For many kinds of parts, there's a substantial gap between specified maximum/minimum timings and typical timings. The 8088 specification requires that the clock be high for a minimum of 69 ns every cycle and low for a minimum of 118 ns. Dividing a 14.3818 Mhz clock by three yields a high time of 69.5 ns and a low time of 139.1 ns, satisfying both ...


18

Quartz used in colour TVs such as 3.579545MHz or 14.31818MHz used to be much cheaper than other frequencies. It was important for home computers and game consoles (8/16 bits), which used the same quartz for video and the CPU, keeping everything synchronous. It was far less siginificant for rather expensive computers such as IBM PC which didn't need to ...


13

The Super NES (SNES) has a much different hardware architecture than the Sega Genesis, and is built around the custom Ricoh 5A22 ASIC. As opposed to the discrete, stock, Motorola 68000 CPU employed in the Sega Genesis/MegaDrive, the SNES ASIC contains multiple components that internally operate at different clock speeds. The ASIC has the 65C816 CPU core, ...


13

To get a faster operation there are several "extensions" around, which are either connected to the extension slot or replacing the CPU on its socket working like a coprocessor. CMD's SuperCPU, Flash 8, and one project from the c't computer magazine (a German one) reborn as follow-on project LTC64. They have all in common using a WDC 65C816 CPU, a 16-bit ...


9

If you're changing just CPU clock speed, leaving the other components as is then amongst those that would continue to read tapes correctly are: The Vic-20 and the Commodore 64. In the case of the Vic-20 tape input is connected to one of the control lines of a 6522 VIA. Wave length determination is achieved by loading a timer on that VIA and checking its ...


9

Since you mentioned the Apple II, it is worth pointing out that accelerators were available for that platform "back in the day". I can speak to how the CPU replacement ones worked (e.g. Zip/RocketChip) since some others simply took over the bus and some did RAM mirroring with faster SRAM which is a bit more complicated than a simple overclock. As with most ...


8

And the main problem here is that in most cases, you'll have to overclock the entire computer, not just the CPU. For example, in ZX Spectrum CPU clock is generated by ULA, so you'll have to overclock it in the first place. In C64, CPU works in tight sync with VIC, so again overclocking CPU means overclocking VIC. And then, once you overclock video chip, ...


6

I think your bigger problem is going to be dynamic RAM refresh. Particularly in Z-80 systems where the CPU controls DRAM timing, overclocking already tight memory timing specs are undoubtedly going to cause glitches.


5

It's an issue of integration. On the early Genesis systems the custom chips and CPU were physically separate from each other so it was easy to isolate the various clock signals and replace the CPU with a part rated for faster operation. The SNES has a more tightly integrated design where an ASIC contains both the CPU and other components, making it harder ...


3

It's doable if you have a lot of time, decent electronics skills, and some good test kit to figure out how the VIC video chip and the 6510 share the address and data bus. If I remember correctly, the 6510 reads/writes in one part of the clock cycle, and the VIC chip reads in the other part. I know this because in 1990 a friend and I made a 4Mhz accelerator ...


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