The technical differences are large when compared to the technical similarities.
CTSS was built for a modified IBM 7094 system while ITS was built for the DEC PDP-6 (later PDP-10). Both of these machines were organized around 36 bit words, but the similarity tails off after that. Both machines lacked a hardware page map, and did not attempt to provide ...
LOGO was intimately tied up with research into educational methods, and in teaching children how to use computers.
The project proposal by Seymour Papert mentions "research on children's thinking and elementary education".
Further LOGO memos are found here.
The question remains is, is this what the language was "originally" for, or was the language co-...
However, at that time, the world had not yet settled on octets.
I beg to differ. If you look through brochures and manuals of next to all manufacturers, they tried hard to be IBM compatible at least for data exchange. Being IBM compatible was effectively mandatory for the whole industry and with the /360 introduction in 1964 the size of a byte (for ...
ARPANET isn't the only context in which the world of PDP-10 computing ran into data paths that used octets for framing. Four other contexts come to mind: 9 track magnetic tape, PDP-11 file exchanges, DECnet, and Kermit.
9 Track Magnetic Tape. 9 Track tape rapidly became the most popular standard as IBM transitioned from 36 bit processors to the 360. ...
It's done by use of the EXCHange instruction with interrupts disabled.
The Long Read
The PDP-10 also allows an interrupt to occur part-way through one instruction, so there's no guarantee that even one instruction is atomic.
Even the PDP-10 could disable interrupts.
How was it done in those days?
The old fashioned way of semaphores to ...
From the MIT AI Lab file .INFO.; LISP ARCHIV for Maclisp updates:
THE CURRENT VERSION OF LISP, "LISP 102", HAS
THE FOLLOWING AS-YET UNDOCUMENTED FEATURES:
1)"DEFUN" IS AN FSUBR USED TO DEFINE
FUNCTIONS. EXAMPLES ARE
(DEFUN ONECONS (X) (CONS 1 X))
WHICH IS EQUIVALENT TO
(LAMBDA (X) (CONS ...
The First Part Done bit is used to signal whether a specific part of an instruction (the "first part") is done already or not.
It is only set on instructions like ILDB ("Increment and load byte") and ILDW ("Increment and load word") that address a pointer to a byte/word in memory, increment that pointer, and then fetch the byte or word that is referenced ...
According to Wikipedia: Logo, second paragraph fragment
The language was conceived to teach concepts of programming related to
Lisp and only later to enable what Papert called "body-syntonic
reasoning", where students could understand, predict, and reason about
the turtle's motion by imagining what they would do if they were the
What are the differences between these? I'm not that interested in architectural differences, cache sizes, etc. I'm most interested in the differences that could feasibly trip up an assembly language programmer.
For user side assembly programmers next to none - at least until the KL. UUOs (*1) did hide add ons for backward compatibility or non ...
36-bit computers were used to communicate through channels which were not 36-bit.
ARPANET packets are not the only one, paper and magnetic tapes, connections to terminals, ... have also their frame which is not 36-bit.
Protocols and OS of the time were used to define various ways to transform 36-bit words in smaller units (search here for SET TAPE FORMAT ...
Seymour Papert was a developmental psychologist, and in the early days of computers had lots of interesting ideas about how children might be taught using them. His work's online if you're interested.
The "real" turtle wasn't like the autonomous robot "tortoise", it was simply a plotter on wheels. A domed robot with 2 large wheels, one per side, that could ...
I'm guessing here, but I suspect they started from Intel's own INTERP/8 8008 simulator. This was supplied on tape for PDP-10 as FORTRAN IV source. While I can't find the source of INTERP/8, the manual is an appendix of this Lawrence Livermore report "SIlMULATOR PROGRAM FOR THE INTEL MCS-8 800 CPU" [PDF]. Intel's simulator for the 8080, INTERP/80, was ...
This is a frame from MIT AI film #43. I'm not sure what year it's from, but it seems to be from the PDP-6 era. The code is very similar to old ITS source code, so it's likely this is a tiny fragment of PDP-6 ITS. The use of "↓₁₄" identifies this as text displayed by PDP-6 TECO.
Transcription, including a few more lines visible in the film:
I don't know if it counts as a 16-bit historical computer, but there were a number of 80287 clones. One of them, from IIT, added a F4x4 instruction that operated on the entire FP stack to perform matrix operations (the IIT chip had not one, but four stacks of eight FPU registers each).
A friend of mine had one of these coprocessors back in the day, and it ...
I'm pretty sure that the KA-10 processor, the first of the PDP-10 processors, had a read-pause-write memory cycle that allowed retrieving and altering a memory location in an atomic operation. Otherwise, instructions like AOSE (Add One and Skip if Equal) would be vulnerable to interrupts. Edit: Also vulnerable to other processors.
Any instruction could be ...
It might be useful in indirect threaded code. This is a contrived example based on my brief 45-years-ago acquaintance with a Snobol4 implementation (Macro Spitbol - Dewar and McCann).
Consider that each statement is compiled into a sequence of 'code objects', each of which contains some standard attributes and also a pointer to the (fixed per type of code ...
This is only a partial answer, and I hesitate to post it because it's going to primarily be a link, but...
There are some real, programmer-visible differences between the PDP-6 and the KA10, though for the most part the KA10 can run code intended for the PDP-6. Here is a pretty comprehensive list of differences - there are just too many to copy into a ...
A (calculated) address (from an instruction) is always used to fetch a word (36 Bit), which, if the I bit was set, is interpreted again the same way - thus allowing indefinite addressing chaining - otherwise used at face value for the operation.
The Long Read:
All instructions always an effective address, usually an operand in memory (*1)
As you ...
I think the big question you have to ask here is: What would such an instruction have been useful for? Single-bit data types don't usually go together with matrix operations.
I've looked at some examples where the MMIX instructions are used, and they don't seem to be very compelling, given the hardware complexity of doing so. For example, if you want a ROL ...
Digital Equipment Corporation designed the hardware for the AOSE (Add One and Skip if Equal) instruction so that NOTHING could interrupt it. Once that instruction started, it finished. Period. It was specifically intended for use as the hardware-based synchronization primitive.
There was a sentence in the processor reference manual that read something ...
Compare memory contents against two bounds:
SKIPG A,FOO ;FOO GREATER THAN ZERO?
CAIL A,BAR ;FOO LESS THAN BAR?
A subroutine can have two entry points loading different values into an accumulator:
ONE: SKIPA A,
TWO: MOVE A,
Convenient way to load ...
I have something to add. It's not exactly an answer, but it's too long for a comment.
You are linking to 11Logo (which I put on GitHub, courtesy of CSAIL), but this wasn't the first version of Logo. It was first implemented on PDP-1 at BBN, and later updated for a PDP-10.
The PDP-10 version was moved to MIT (the files still have a BBN copyright notice), ...
Phil Budne’s list of TOPS-10 versions is the most comprehensive list I’m aware of, from TOPS-10 5.01 in 1970 (the first release with the “TOPS-10” name) to 7.0 releases with uncertain version numbers in 1990. Before 5.01 it was called the “Monitor” (PDP-6 Monitor on the PDP-6, then PDP-10 Monitor on the PDP-10), and some of those releases are included in ...
There are two reasons to have this group of instructions actually load the value that you're comparing.
The first is that the instruction word has a field that specifies an accumulator anyway, and the instruction set is very orthogonal so it only makes sense that a compare instruction also references an accumulator. The skip instructions compare a value to ...
It's possible to try both CTSS and ITS yourself. Both operating systems run on emulators.
As for differences, Tom Knight, one of the ITS creators, wrote:
I would actually say that the main influence of CTSS on ITS was a demonstration of just what it was that we didn't want to do.
See more here: https://github.com/PDP-10/its/issues/1588
Execution of all PDP-10 instructions first involves the computation of an "effective address" E. This computation is identical for all instructions, regardless of how they will use the result, and regardless of whether it's actually going to be used as an address, or used at all. The instruction format contains 3 relevant fields: Y (an 18-bit value), X (a 4-...
Just a quick supplement to the other answers.
The PC does not get pushed automatically. When an interrupt happens, the processor operates in a special mode where instructions are fetched but the PC stays the same as before the interrupt. If you want the PC saved (which is not always necessary), you should use a JSR instruction to explicitly do that.
IIRC, this was set during very CISC-y instructions that could take many dozens of machine cycles and/or memory accesses. It was set so that if a page fault or other high-level interrupt occurred while the instruction was executing, the CPU would know not to restart the instruction from the beginning (although I'm a little hazy about how it knew where to ...
A DECtape labelled TS9 has been round in Richard Greenblatt's house. Given other labels found in the RG; FD 4/1/68 file, it's likely it would have a copy of PDP-6 ITS.
The tape has been imaged and analyzed. There are files from ITS, but not ITS itself.