45

Yes, BASIC is much slower than assembly for many operations. For an easy example, try out this program on a Commodore 64 or emulator: for i = 1024 to 1984 : poke i,peek(i) or 128 : next You will see each character on the screen reverse, row by row, over the course of ten seconds. By contrast, the exact same routine in machine language inverts the entire ...


31

Both processors are cacheless. So the process is fetch instruction, decode instruction, execute instruction, forget what you saw. That provides a first line of comparison. The Z80's fastest memory fetch — the first half of an operation fetch — takes two cycles. That's always paired with another two cycles for refresh though, so the shortest instructions are ...


27

There's no real optimisation — LDIR (or indeed LDDR, which goes downward instead of upwards) is the complete inner loop. It will always load from HL, store to DE, increment both and decrement BC. Then if BC is non-zero it will repeat. Annoyingly it will repeat exactly by just decrementing the PC by 2. So it'll read the full instruction again. Which means ...


27

If you look at the datasheet of a typical DRAM chip of this era, say the Mostek 4116, it indeed has a cycle time of 375ns, so you can't access it at more than 2.6 MHz. But don't confuse the clock rate of a microprocessor with the bus timing. Looking at figure 4-1 of the 68000 datasheet, a simple byte read or write bus cycle takes 4 CPU cycles (8 bus states; ...


26

Classic RISC CPUs like ARM ... instructions execute in one cycle ... This assumption is not correct. The ARM-2 CPU (VL86C010, one of the first ARM CPUs) took: Only one cycle for most operations (as you expected it) Typically two cycles if a jump/branch was done Up to 4 cycles for shift/rotate operations Up to 16 cycles for multiply operations Up to 17 (or ...


25

No. In your hypothetical 16 bit machine with 64kiB of RAM, you could simply implement two 32kiB banks with using sixteen 16kib chips each. This obviously doubles the required number of chips and board space required, which may not be cost-effective against using just next higher-density chips and getting twice as much memory again for free. At least one ...


17

Does fast page mode apply to ROM? No. Why should they? You're missing one step to start with in your chain of thoughts. (Fast) Page Mode is an improvement to the address multiplex protocol dynamic RAM uses. As such it isn't a general improvement, but a relative one, reducing the overhead the address multiplexing implies. Address multiplexing was ...


16

It has been already done for ZX spectrum. see Velesoft: DATA-GEAR It has DIL40 socket compatible pins at the bottom and it replaces Z80 (so the bus is as short as possible). According to that site The bandwidth is around: ZX128+ is 17.3 kB(17727 bytes) / frame = 865.6 kB(886350 bytes) / second The higher bandwidth allows: fast scrolls MultiTech techniques ...


16

Most implementations of BASIC for 8-bit home computers were interpreters, and in that sense they're similar to the standard versions of Python. You could typically expect simple programs to run 100 times slower in BASIC than in assembly of ordinary quality. However, it would normally take much less time to write that program in BASIC than in assembly. For ...


15

There are nearly endless benchmarks (see a short list of relevance at Benchmark Programs and Reports on the Top500 site) and it may need a bit of work to understand each benchmark's implications (see Benchmark Tutorial, in IEEE Micro 1989, or An Overview of Common Benchmarks in Computer 12/1990). Benchmarking will always give only a rough estimation, so all ...


15

Naïve programming was often limited by memory speed even for the fastest mainframes available in the 1980s. For example on an IBM S/370 system, the maximum amount of memory available to a single user program could be limited to about 9MB out of an address space of 16MB (the other 7 being reserved for the operating system!) compared with hundreds of MB of ...


15

I've been thinking about something like this myself, recently. I wasn't planning on using a Z8410, though, but an Intel 8257-5. This has a number of advantages: It has 4 controller channels rather than 2 It was actually a cheaper chip than the Zilog chips The interfacing to the Z80 wouldn't be quite as easy, but fundamentally the Z80 and the Intel 8085 ...


14

Memory hasn't always been the limitation. IBM identified (and in many ways, encouraged the adoption of) two kinds of computing: scientific and data processing. Data processing computers (such as the IBM 702 from 1953) had relatively modest processor power, but enough memory to hold all the parameters for the day's business transactions to ensure that ...


14

The documented execution times count the cycles required to execute the instruction itself, including any memory accesses caused by the instruction, and ignoring everything else. The Intel manuals provide pseudo-code showing what each instruction does; you can consider that the cycle counts cover that, only. Thus in CBW’s case, the iAPX88 manual shows: if (...


14

There were several variations largely driven by cost at any particular point in time. What is interesting is WHY 1 bit chips were popular, basically your address bus was typically multiplexed using the RAS and CAS signals, so if the technology at the time made 64K a desirable chip size, you could do 8 Address, RAS,CAS, 1 Data, WR, RD, CE plus power and ...


14

the drive could end up only being able to transfer one bit per horizontal blank = 63 microseconds. 1/(63e-6) = 15873 bits/s = 1984 bytes/s. That would be the bitrate during transmission within a byte, but bytes are framed and handshaked, which adds an average of 160 µs per byte. Resulting in (63 * 8) + 160 µs, or ~664 µs per byte. So the upper transfer sped ...


14

Not a complete answer, but a bit of information from the manual (for several Novas including the 1200): The hardware multiply-divide option for the Nova is actually a peripheral device connected to the in-out bus, although it has no flags or interrupt capability. It contains A, B and C registers, which are loaded and read by the standard IO transfer ...


13

I think you've let your understanding of the situation as it was in the late 70s/early 80s become somewhat more simplified than it actually was. For example: RAM chips of the late seventies and early eighties could do 2 MHz (or a bit more e.g. 2.6 in the datasheet I found) You say you're looking at a 16K design, so it's highly likely it'd be based on ...


13

DRAM access in general and page mode (*1) in particular are not CPU features, but depend on the DRAM controller. No matter if build by discrete components (like mulitiplexers and counters) or dedicated IC. Pagemode DRAM can be used with any CPU if the controller (access logic) used supports its features. No matter if it's an 8080 or a 68020. You won't find ...


13

The Amiga A500 used 41256-15 DRAM chips for its onboard memory. According to the datasheet these had a cycle time of 260ns, so could easily match the 280ns timing constraint with 20ns to spare (although the board had two banks of them, and switching between the banks likely used up most of that 20ns). The 375ns limit really only applied to the 4116 and ...


13

[I]s there ever a circumstance where Mode 13h is a better choice for fast scrolling DOS games over Mode X? Sure, to start with, any single pixel operation on in Mode X is slower than for Mode 13, as the desired plane needs to be set first (*1) Next, the latch-trick (*2) can only move horizontal by 4 pixels at once. So any horizontal scroller will be ...


13

On paper, based on the fill rate only, all the high-end graphics adapters available on PC in 1999 were at least as powerful as the Dreamcast’s PowerVR2: the CLX2 in the Dreamcast ran at 100MHz, with one operation/pixel/texture per clock, and memory bandwidth of 0.8GB/s; the PMX1 (PC-compatible PowerVR2) ran at 125MHz, again with one operation per clock, and ...


12

The Whetstone table may be useful. The ratio of Whetstones/s to FLOPS varies, but not too much. A whetstone test outputs a table, like Loop content Result MFLOPS MOPS Seconds N1 floating point -1.12475025653839100 19.971 0.274 N2 floating point -1.12274754047393800 11.822 3.240 N3 ...


11

A typical EPROM series of that period is the 27xx series. Today's DIL EEPROMs still use the same pin layout. Access time varied with models. Datasheets with exact dates are difficult to google systematically, but for example, an Intel 2764A-250 had a 250ns access time in 1983, while the 2764A-1 variant had a 180ns access time in1989. So the ballpark is "...


11

The 6502 situation isn't quite that rosy — the Vic-20 has a 12-bit data bus so that it can fetch both pixels and colours during its gap, the C64 has a complete CPU lock-out for the first row of every character line, the Atari 400/800/etc use a special modified 6502 on which they can stop the clock to get the CPU out of the way, the Oric runs the 6502 for ...


10

Perhaps I should just edit the contradiction out of the accepted answer that starts by claiming you can do no better than LDIR then mentions that unrolling it to a series of LDI instructions is faster. But for the nonce I'll put an explicit example of the LDI unroll here. ; Copy BC bytes from HL to DE. copy_mem: ld a,b or c ret z ...


10

Pushing large chunks of bytes around is actually a task a DMA chip is very good at. The point is: Pushing partial bytes around is a task a DMA chip doesn't help sooo much, there is a lot of the job still left to the CPU. A DMA chip is not capable of shifting the bits in a byte, which was one of the main operations when handling retro computers sprite ...


10

Generally speaking, Z80 is two to three times slower than 6502 since its fastest instruction is 4 cycles and 6502's is just 2. Then, if you take into account additional instruction bytes and memory addressing, Z80 looks like it's completely behind. But things in real life differs a bit. Z80 has more registers (7 primary, 7 secondary and 4 additional that ...


10

In general most instructions on the 6500 series take as many cycles as there are memory accesses, with a lower limit of two. This means no instruction will execute in less than two cycles (*1). The mentioned ADC gives a nice example, as it offers almost all addressing modes: Mode Example Length | Cycles ...


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