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24 votes
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When did the PC bus start slowing access to video RAM?

This question starts with a number of misconceptions about early video, memory and bus systems that need to be addressed in order to clarify what this question really appears to be about. If you want ...
cjs's user avatar
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16 votes
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What did it cost the 8086 to support unaligned access?

The Missing Angle It feels a bit like the question misses the most important point about the whole 8086 project over discussing implementation details: 8080/85 compatibility The 8086 was intended as a ...
Raffzahn's user avatar
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15 votes

When did the PC bus start slowing access to video RAM?

TL;DR: When the CPU-bus became faster than the I/O-bus Now, there are always going to be wait states during active scan line, because the video chip is using some of the video memory bandwidth for ...
Raffzahn's user avatar
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11 votes

When did the PC bus start slowing access to video RAM?

The original CGA always imposed wait states on display memory accesses. The card's memory subsystem always performs one access every four pixel clocks, and only half of those are available to the CPU ...
supercat's user avatar
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9 votes
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Maximum speed of serial I/O bit-banged by 8-bit CPU

Well there is no simple answer. If you assume that the CPU runs undisturbed, you can just count the cycles and that's how many systems already handle their tape storage, you just seem to want higher ...
Justme's user avatar
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8 votes

Relay computer performance

Well, a good datapoint here may be the Zuse Z3 and Z4 computers. Not at least as their workings are close related to today's computers in being tact controlled as well as using binary floating point ...
Raffzahn's user avatar
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6 votes

Maximum speed of serial I/O bit-banged by 8-bit CPU

There are so* many misconceptions in that question, it's hard to know where to start. The issue with IEEE-488 was absolutely nothing to do with it being parallel, and everything to do with it being a ...
Graham's user avatar
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6 votes

Maximum speed of serial I/O bit-banged by 8-bit CPU

Hmm...at least offhand, it seems like you need around 4 instructions per bit and a Z80 needs at least 4 T cycles per instruction. Along with that you need to load the next byte from memory once every ...
Jerry Coffin's user avatar
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5 votes

When did the PC bus start slowing access to video RAM?

Actually, if you carefully read the BIOS for the IBM PC and CGA video (I did), you will find that (at least in text mode) it delayed every access to the video memory until the display entered a ...
David G.'s user avatar
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4 votes

Maximum speed of serial I/O bit-banged by 8-bit CPU

On the 6502, a lot depends upon the placement of the bits in whatever I/O register is being used or--for reception--if one bypasses the use of an I/O register entirely. The fastest reception from a ...
supercat's user avatar
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1 vote

Maximum speed of serial I/O bit-banged by 8-bit CPU

Bit-banging by processor would be the exception, rather than the rule; 8 bit shift registers weren't that rare or expensive. (But bit banging the tape port was fairly common, as this could be done ...
hawk's user avatar
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