New answers tagged performance
10
In general most instructions on the 6500 series take as many cycles as there are memory accesses, with a lower limit of two. This means no instruction will execute in less than two cycles (*1).
The mentioned ADC gives a nice example, as it offers almost all addressing modes:
Mode Example Length
| Cycles
...
9
Assuming you’re asking: what can the 6502 be seen to be doing by an external observer, then the data sheet has a full breakdown of bus activity per cycle per addressing mode; that was long ago transcribed into ASCII form by the Commodore community and is now often sourced from that 64doc.txt.
Do a search in that document for “Instructions accessing the stack”...
2
The length of the ADC Immediate is 2. One for the opcode $69 and one for the immediate. At the very least, this requires two bus cycles to fetch. On a "simple" processor, an instruction can't take fewer cycles than the number of bus cycles that need to be performed to do the work of that instruction.
12
Not a complete answer, but a bit of information from the manual (for several Novas including the 1200):
The hardware multiply-divide option for the Nova is actually a peripheral device connected to the in-out
bus, although it has no flags or interrupt capability. It contains A, B and C registers, which are loaded and read by the standard IO transfer ...
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