Less historical example: ARM (Advanced RISC Machines...) Cortex-M4 has many (though a clear minority) instructions that execute in more than one cycle.
See this list:
Cycle count gets less clear when pipelining or dual-issue is introduced (like in the Cortex-M7)
I'm sure there were plenty of early "RISC" engines which took on the order of 8 cycles per instruction. One cycle to fetch the instruction, one to access the registers, one to store the result, one to increment the instruction counter. That's 4, but the fetch may have taken several.
(In case anyone's wondering, I was in meetings with George Radin ca 1975.)...
To start with, cycles, especially cycles in term of some external clock source aren't really a good measurement at all. Already with the mentioned 6502 internal workings are tied to two clocks effectively doubling the clock rate the chip works at (PHI0->PHI1/2). Something easy to see with the Visual 6502 simulator.
Next, as Martin Rosenau has shown, even ...
Classic RISC CPUs like ARM ... instructions execute in one cycle ...
This assumption is not correct.
The ARM-2 CPU (VL86C010, one of the first ARM CPUs) took:
Only one cycle for most operations (as you expected it)
Typically two cycles if a jump/branch was done
Up to 4 cycles for shift/rotate operations
Up to 16 cycles for multiply operations
Up to 17 (or ...
One RISC CPU I know of is included in the PIC microcontrollers:
I happen to have an old General Intruments data book that says the oscillator clock is divided by sixteen for some part, and by four for some other part.
The well-known 8-bit PICs by Microchip divide their system clock by four into instruction cycles.
However, there were clones that run at ...