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32

Despite the 144 pin DIMM form factor, this is not a SDRAM, but an EDO module with 16 MiB capacity. The used RAM chips are KM48C2104 (KM48 marks RAMs) Manufactured by Samsung, of 16 MiBit Capacity EDO-RAMs, with 2Mi by 8 Organization and 60ns speed (the -6 marking) They are not SDRAM, as such would be numbered as KM48Sx with X being L for 66 MHz and H for ...


29

PIC: 7 bit address space The Microchip PIC family of CPUs specifically the 10, 12 and 16 series have 7 bits of address space. While 7 bits is not exactly 8 bits this shows that there are commercial CPUs still on sale and still widely used that have less than 8 bit address space (they are used for example for power management on some Macs and are the most ...


26

Here is a reference to BIOS beep codes. For American Megatrends, look under AMI. 3 beeps means the low 64K failed - a very basic test - which probably means the RAM isn't working at all. You should first check whether the RAM is compatible with your machine. At that time, there was a lot of variation - 5V vs 3.3V, 30-pin vs 72-pin, EDO vs FPM, not to ...


24

Simple reason: Commodore had an overstock of 2114 Chips at that time (*1), so Jack Tramiel, then president of Commodore, ordered the project (*2) to use them. Yeah, but why 5 KiB? Why not just 4KiB? Due the nature of the 6502, RAM is needed at address 0, while the way the 6560 VIC (*3) was addressed called for RAM at $1xxx. So with a continous memory of 4 ...


24

The KENBAK-1 has 256 bytes of memory. I'm not certain whether it had an 8-bit PC. https://en.wikipedia.org/wiki/Kenbak-1


24

The Apple III came with a minimum of 128K of RAM (expandable to 512K) two years before Commodore had a series of CBM-II computers with 128K minimum and expandable to 896K in 1982 a year before the IBM PC XT and 2 years before the Apple Macintosh and IIc. The IBM PC had 64K minimum. 1980: Apple III 1982: Commodore CBM-II 500 / 600 / 700 Series 1983: IBM PC ...


22

Well, it's a 'trick' to simplify the editor as well as the BASIC editor. After Reset (or NEW) three bytes of Zero are placed at the beginning of the basic RAM. They make it look to the basic interpreter as this looks like the tokenisation of a single, empty BASIC line. Consisting of One byte 00 as line end marker and Two bytes 00 as pointer to the next ...


18

Because there were spare pins otherwise. Because sometimes this could make the design simpler. As an example, I'll put again schematics of a russian ZX clone, for example this one, named "Leningrad". All other clones with single DRAM set are made in a similar way. The inputs of DRAM chips (D21..28, labelled as 565RU5 -- russian analog of 4164) are ...


18

Sinclair's use was a very unique case in a very specific situation that never occurred again later on. Production side: There were many more manufacturers of chips back then. The ones that wanted to compete at the forefront used RAMs as gateways to technological development. (*1) Anyone not ramping up their output fast into the upper 90s will lose money. ...


16

The daughterboard is the graphics card. The GD610/GD620 is a quite common chipset for LCD/VGA graphics in laptops. It uses two 64k x 16Bit RAM chips to obtain 64k x 32Bit, which is the usual VGA memory (256 kBytes, but the VGA needs 32-Bit access to get the data fast enough to the screen). Those RAM chips have an access time of 100ns. The chips on your ...


15

Most of the reference material for the Apple II that I have seen refers to the 4116 RAM chip which held 16x1 kbit. Jup, at the time the Apple II really took off, 4116 chips had already dropped to less than twice the price of 4104, making any use of 4104 impractical. Not many were delivered using 4104, and while some users may have had 4104, they all soon ...


14

Intel manufactured its 1-kilobit 1103 RAM on an 8 μm P-MOS process. Through most of the 1970s, DRAM was made from NMOS. The first successful CMOS memory was the Hitachi HM6147 SRAM, a 4-kilobit chip which used a 3 μm CMOS process. This was not the first 4-kb chip on the market (it was preceded by, among others, the Intel 2114 SRAM), but it’s more comparable ...


13

How two 260ns RAM accesses could fit in 500ns? By using a 250ns (*1) tRC cycle? And yes, strictly that's out of spec. Still chances are very good that each and every chips will make it, as the timing range selected is rather conservative to start with. Even more so as this value is usually defined by the makers as being guarantied over the the whole ...


13

Your observation about the 64K address space is correct, your 32K RAM and 32K EEPROM will be able to fill that address space to 100%. In Z80 designs, the ROM/PROM/EPROM/EEPROM is usually placed starting at 0x0000 since when you do a RESET, the Z80 starts executing at 0x0000 and you usually want to have your program start there. Of course there are many ...


13

The year you've picked has a strong influence on the answer. By 1999, most new games were being released to run under 32-bit Windows using DirectX, and were therefore running in a demand-paged multitasking virtual memory system. This has two consequences: Checking available memory was no longer necessary - if you didn't have enough, the OS would emulate it ...


13

Finally designed and built an Amiga A1050 knockoff. Seems to work well on my Amiga 1000. Schematic, PCB and BOM is posted on github https://github.com/TheOrangeStrain/Amiga-A1050-RAM-Expansion The answers to my question are: The black blob is indeed a 39 ohm resistor pack C1-C8 are 0.22 uf capacitors C9 is a 10 uf capacitor Thank you to those who gave me ...


13

Soviet: ES PEVM (IBM PC clone) - 1986 Okean-240 (128 KB, Intel 8080 class) - 1986 UKNC (192 KB, PDP-11 class) - 1987 DVK-3M (248 KB, PDP-11 class) - 1987 Korvet (112-256 KB, Intel 8080 class) - 1987 BK-0011 (128 KB, PDP-11 class) - 1989 Poisk (IBM PC clone) - 1989 Iskra-1030 (IBM PC clone) - 1989 Agat (Apple clone) - 1989 Bashkiria-2M (128 KB, ...


12

The first that comes to mind is Cypress' M8C core used in the PSOC-1 series. While it has a 16 bit program address space (and thus 16 bit jump instructions), its data as well as the register space are each strictly 8 bit. Implementations do use up to two sets of 256 registers and may offer several sets of 256 Byte banks. From the manual: The M8C is an 8-bit ...


11

[...] Commodore 64 did indeed provide 64K of RAM [...] only 38K was usable from BASIC; [...] bank switching was needed to get at the rest, And that's exactly the way the TED computers did use. but if a BASIC program switched out the [...] ROM, [...] it would of course promptly crash. Well, BASIC 3.5 was aware of that and did provide functions for various ...


11

I did find some prices in BYTE: November 1975, page 91 2107 4Kx1 Dynamic: $19.95 (0.49 cents/byte) 2111 256x4 Static: -- not listed 1101 256x1 Static: $2.25 (0.89 cents/byte) April 1976, page 89 2107 4Kx1 Dynamic: $19.95 (0.49 cents/byte) 2111 256x4 Static: $7.95 (0.77 cents/byte) 1101 256x1 Static: $2.25 (0.89 cents/byte) Byte ...


11

Not strictly an answer, but some early computers had very limited addressing. The Harwell Dekatron computer, which operates entirely in decimal, has an address space of 100 words, of which 90 are RAM and the other 10 are devices. Programs for it are usually run directly from a paper tape device (where the tape, rather than the PC register, is advanced after ...


10

"The console" (or other computer) is made up of various parts, including the processor, the memory, and peripherals such as video display controllers, I/O chips to read from a keyboard or joystick, disk controllers, and so on. When using "programmed I/O," the CPU reads data from or writes data to a peripheral and, if the data need to be stored in memory, ...


10

The XMS api doesn't support as much memory as you have installed - it uses 16 bit registers to specify memory sizes in units of KiB, so the maximum amount of memory it can report to a program that queries the available memory is just under 64MiB. Windows 98 generally expects applications to use DPMI to request memory rather than XMS, which was only included ...


10

Can anyone explain how separate data inputs and outputs for RAM would be useful for a computer system designer? There are several advantages: Design: Timing is only defined by address transfer No additional requirement for access timing Outputs is static, only defined by address input No specific bus structure required Any bus adaption (latches, buffers) ...


10

Sure, it works, but then again, why decoding four 16 KiB blocks when it's about two 32 KiB chips? All you need to decode is A15. A15=LOW should select the ROM (*1), while A15=HIGH does the same for RAM Inccoperating a A14 is rather pointless and using a'139 looks like overkill unless there is some future use. It also adds signal time, limiting maximum ...


10

[Please see as well this answer, as it's kind of an extension] Why did IBM 7030 or IBM 360 use byte and word addressing simultaneously Not sure what's with /360 reference here, as it's uses byte addressing (*1). The 7030 in contrast used word and bit addressing. Word addressing of 18 bit when it was about words, and bit addressing in the form of a 24 bit ...


10

Because the PS1 has a very small amount of RAM, and sophisticated games, especially those on linear tracks like Crash Bandicoot, would load new data from the disc continually as the player traversed the level, replacing the data in RAM that was already there. When the player dies and reappears at an earlier location, the level would have to be reloaded from ...


9

The garbled screen is normal on startup, but should be replaced by the BASIC screen after a moment. There's a rather detailed troubleshooting guide, including links, at http://www.dasarodesigns.com/projects/troubleshooting-common-problems-with-the-commodore-pet-2001/ I'd suggest that you ignore the spare parts sales pitch at the beginning and work your way ...


9

What's the question? First problem here is what is to be considered speed. Random access time? Cycle time? Maximum memory thruput? Average memory thruput? Either value per chip or for the whole memory subsystem? For the following I'll go with maximum memory band for the whole memory subsystem. That is when a memory page is opened and successive access is ...


8

The following information comes mainly from pages 70-72 of the Apple II Reference Manual, 1979 edition. The Apple II had three rows of eight sockets for DRAM: rows C through E from front to back. Each row could accept either 4116 16Kbit×1 or 4104 4Kbit×1 DRAM chips. Each row also had next to it a DIP socket for a 14-pin "memory configuration block" ...


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