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37 votes
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Have there been any instruction sets with an odd register width?

Below are some architectures with odd word sizes: Apollo Guidance Computer: 15-bit Autonetics D-37C Minuteman II Guidance Computer: 27-bit Electrologica X1, Electrologica X8: 27-bit Calcomp 900: 9-...
phuclv's user avatar
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34 votes
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Why was segment register value scaled by such a small factor of 16 on i8086?

Wikipedia says: According to Morse et al.,.[5] the designers actually contemplated using an 8-bit shift (instead of 4-bit), in order to create a 16 MB physical address space. However, as this would ...
tofro's user avatar
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28 votes
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How were the test registers used on the i386 and the i486?

The 486 test registers are described in the i486 Processor Programmer’s Reference Manual, starting on page 10-8. The 386 test registers are a subset. Registers TR6 and TR7 provide access to the TLB. ...
Stephen Kitt's user avatar
23 votes
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PDP-11 Program to Execute Only in the Registers

In the PDP-11/05,11/10 computer manual (DEC-11-H05AA-B-D, section 10.5, page 10-3) DEC describes how the PDP-11/05 can execute short programs out of scratch pad memory (SPM or simply SP). Scratch pad ...
Jay Logue's user avatar
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20 votes
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Can PDP-11 general registers be referenced by memory addresses?

Most PDP-11 models can use the addresses listed to examine the registers from the console (subject, of course, to the capabilities of the hardware: not all PDP-11s have two register sets, not all PDP-...
dave's user avatar
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20 votes
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Why do only the low 7-bits of the R register increment?

The R register is solely used to put out consecutive increased row addresses for RAM refresh. The fact that it is readable and setable by programs (*1) is rather a quirk than a feature (*2). I and R ...
Raffzahn's user avatar
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20 votes

Have there been any instruction sets with an odd register width?

The EDSAC (started in 1947) had been intended to have 18-bit words, but due to timing difficulties in the mercury tanks, it ended up with only 17 (= 18 - 1) bits usable for word operations, or 35 (= ...
dave's user avatar
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17 votes

Have there been any instruction sets with an odd register width?

The Elliott 803 computer was 39-bit. The instructions are 19-bit with two per word plus a single bit modifier for the remaining bit. Elliott 803 Wikipedia
Kevin White's user avatar
13 votes

Have there been any instruction sets with an odd register width?

To touch on the underlying question: I do not see a reason why this has to be so. There is none. Register width is selected for 3 basic reasons: Fitting the purpose by being able to hold (usually ...
Raffzahn's user avatar
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13 votes

Why do only the low 7-bits of the R register increment?

The 'R' register increment happens simultaneously with other operations, as it happens for every instruction, but must occur after the refresh cycle in each instruction (which happens at the end of ...
Jules's user avatar
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12 votes
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Why when outputting registers' value the result is a wrong fluctuating value in a Z80 CPU?

I/O port data should be latched by the I/O device on the rising edge of /WR signal. On the falling edge, the only thing that is stable is the I/O port address. EDIT: just noticed you said you are ...
mcleod_ideafix's user avatar
10 votes

Why was segment register value scaled by such a small factor of 16 on i8086?

Using a scale factor of 16 means makes it convenient to work with objects up to 65520 bytes located on any 16-byte boundary. High-level languages don't support the concept very well, but when using ...
supercat's user avatar
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8 votes
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What is R register and DRAM refresh internal operation

DRAM memory is accessed in rows and columns with a multiplexed address bus with row and column addresses sent separately. The DRAM chips used, e.g. TI 4116, were organized as 16384 addresses of 1-bit ...
Justme's user avatar
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8 votes
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What's the minimum number of tubes per bit required to store a register?

The Manchester Small-Scale Experimental Machine used two Williams–Kilburn tubes to hold its registers: one stored a 32-bit accumulator, while another stored the current 32-bit instruction and the ...
scruss's user avatar
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8 votes

Why do only the low 7-bits of the R register increment?

@Jules's link to the incrementer details offers an unsatisfying explanation: When the Z-80 was introduced, 16K memory chips were popular. Since they held 2^14 bits, they had 7 row address bits ...
Jeremy's user avatar
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7 votes

Have there been any instruction sets with an odd register width?

If you are into art, you may have heard of the MIX computer from The Art of Computer Programming. Its words are 5 bytes (not like any other architecture's bytes) plus a sign. So are registers A and X....
30tah8uu's user avatar
7 votes

Have there been any instruction sets with an odd register width?

Great historical examples here, but I missed the one-bit slice processors that were developed in the 1970-s, that went on to the (Intel) four-bit and 8-bit processors that are better known. One (1) is ...
Roland's user avatar
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7 votes
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Confusion in the VIC-II registers

[All following references are in relation to the Archive.Org copy of the Commodore 64 Programmer's Reference Guide ISBN 0-672-22056-3] VM13 VM12 VM11 VM10 CB13 CB12 CB11 -- VM13..VM10 define the ...
Raffzahn's user avatar
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5 votes
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Is scratchpad register 15 directly addressable on the F3850 (except as QL)?

As pointed out in the comments to my question, the VESWiki opcode table I linked to only defines operations for scratchpad registers 0 through 14. So it is in fact consistent with the F8 Guide to ...
tobiasvl's user avatar
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5 votes

Why when outputting registers' value the result is a wrong fluctuating value in a Z80 CPU?

It's possible that on the CPU you have the program counter (PC) and internal status register (for HALT) are implemented using static latches (SRAM) whereas, e.g. the bus drivers are using dynamic RAM (...
Alex Hajnal's user avatar
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3 votes
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Transfer between bus and register in 6502 CPU

If the SB/X (load) signal and X/SB (bus enable) signal are both asserted at the same time, what happens? You mean beside the fact, that it would need a useful instruction based on that function? ...
Raffzahn's user avatar
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2 votes

Have there been any instruction sets with an odd register width?

Zuse Z22 from 1955 (one of the first computers built in series) had 38 bit wide architecture with 38 bits wide registers. https://en.wikipedia.org/wiki/Z22_(computer) edit: upps, you meant odd like in ...
Patrick Schlüter's user avatar
2 votes
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How are the index registers on the Censor 932 accessed?

After having spoken to one of the engineers on the team that built Censor 932, the index registers are R1 to R7, and a "0" index means "do not index".
Vatine's user avatar
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2 votes

Why was segment register value scaled by such a small factor of 16 on i8086?

I don't think your scheme is any more extensible than Intel's. It's easy to see how to widen the address space in Intel's scheme: just increase the shift value in later generations. Of course, this ...
benrg's user avatar
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