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33

Wikipedia says: According to Morse et al.,.[5] the designers actually contemplated using an 8-bit shift (instead of 4-bit), in order to create a 16 MB physical address space. However, as this would have forced segments to begin on 256-byte boundaries, and 1 MB was considered very large for a microprocessor around 1976, the idea was dismissed. Also, there ...


16

The R register is solely used to put out consecutive increased row addresses for RAM refresh. The fact that it is readable and setable by programs (*1) is rather a quirk than a feature (*2). I and R is a register pair right beside PC; a clever trick to save circuitry: Firstly, I needs to be placed on the upper address bus, like PCH, so putting it alongside ...


12

The 'R' register increment happens simultaneously with other operations, as it happens for every instruction, but must occur after the refresh cycle in each instruction (which happens at the end of instruction fetch, thus pushing the only time the increment can actually happen into the time when the fetched instruction is executing), so it cannot use the ...


11

I/O port data should be latched by the I/O device on the rising edge of /WR signal. On the falling edge, the only thing that is stable is the I/O port address. EDIT: just noticed you said you are clocking your Z80 at 7 Hz. By the picture you have posted, you are using a NMOS Z80 (Z0840004PSC. CMOS Z80s start with Z084C.....). These cannot work below the ...


10

Using a scale factor of 16 means makes it convenient to work with objects up to 65520 bytes located on any 16-byte boundary. High-level languages don't support the concept very well, but when using machine language, rounding object sizes to 16-byte multiples makes it possible to use two bytes for object addresses rather than four. If the scale factor were ...


5

@Jules's link to the incrementer details offers an unsatisfying explanation: When the Z-80 was introduced, 16K memory chips were popular. Since they held 2^14 bits, they had 7 row address bits and 7 column address bits. Thus, a 7 bit refresh value matched their need. Unfortunately, this rapidly became obsolete with the introduction of 64K memory ...


5

As pointed out in the comments to my question, the VESWiki opcode table I linked to only defines operations for scratchpad registers 0 through 14. So it is in fact consistent with the F8 Guide to Programming. I also found another source confirming this, the Mostek 3870/F8 Microcomputer Data Book (the 3870 was the single-chip implementation of the 3850, and ...


5

It's possible that on the CPU you have the program counter (PC) and internal status register (for HALT) are implemented using static latches (SRAM) whereas, e.g. the bus drivers are using dynamic RAM (with no refresh). That would explain why instructions that only depend on the PC (NOP, JP) or status register (HALT) work properly but OUT instructions fail (...


2

After having spoken to one of the engineers on the team that built Censor 932, the index registers are R1 to R7, and a "0" index means "do not index".


2

I don't think your scheme is any more extensible than Intel's. It's easy to see how to widen the address space in Intel's scheme: just increase the shift value in later generations. Of course, this will break software that tries to do arithmetic on segments assuming that the addressable space is and always will be 1 MiB, instead of treating them as opaque ...


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