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57

If you try translating C into Z80, you'll see that Z80 index registers and stack don't behave quite as you expect. So, let us begin with Arrays Suppose you have a standard C construction int c[10]; for (int i=0; i<10; i++) c[i]=0; Your compiler is pretty much required to use 16-bit value for i. So, you have &c somewhere, maybe even in your ...


56

Quite often people don't know how to use the compilers or don't understand fully the consequences of code they write. There is optimization going on in the z80 c compilers but it's not as complete as, say, gcc. And I often see people fail to turn up the optimization when they compile. There is an example here in introspec's post that I am not allowed to ...


56

There are many issues here. As it is already said in comments, decoupling capacitor is a must! 555 (non-CMOS) timer output is very much like the output of TTL ICs, however Z80 requires a firm logic one. When feeding Z80 clock pin from a TTL output, you should use pullup resistor of 200..500 Ohm. NMOS Z80 uses dynamic logic, that means it has some minimal ...


52

For the most part the Z-80 extends the 8080 instruction set. If we consider just the 8080 instructions themselves there are a few incompatibilities: Overflow flag. On the 8080 bit 2 of the flags register only reports the parity of the accumulator after an ALU operation. On the Z-80 it reports parity for logical operations and overflow for arithmetic ...


52

The main downside of "historic" CPU's (non?)-suitability for C programs is the lack of capability to form more than one register into an address without using the ALU. Most more modern CPUs can use base + index + offset register addressing modes to address complex data structures like arrays and structures - The Z80 needs to painstakingly go through the 4-...


50

A number of computers shipped with the Z80B, including: Brascom BR1000M IPTVT TIM-S (Romanian ZX Spectrum clone) M.G.T. Sam Coupé Osborne Executive Panasonic FS A1 WX (MSX) Sharp MZ-2500 (SuperMZ) series Vector Graphics Vector-3 (VIP) Upgrades to the Z80B were available for some computers: Acorn Z80 Second Processor for the BBC Micro


47

One language that was popular on early 8-bit micros, including those that used the 6502 CPU, was Forth. Forth is exceptionally good for this use case, and superior to a C compiler, because Forth can make more efficient use of the 6502's hardware stack. Forth lacks any sophisticated methods of dealing with parameters. Everything is passed through the Forth ...


45

Sinclair didn't always use the Z80 for its computers. The MK14 computer, sold in kit form (like the ZX80 was), used a National Semiconductor INS8060. The ZX range of home computers have a video display hardware that is very closely tied to the architecture of the Z80. On the two first models, ZX80 and ZX81, the video display hardware was kept to a minimum, ...


44

It appears that A0 through A6 operate correctly, but A7 though A9 (I've not tested the rest of the upper bits) are only active on the clock edge. Doesn't that exactly look like refresh cycles? :)) Basic Z80 bus behaviour, here especially the M1 cycle: Z80 timing is structured in Machine cycles (M-states). A machine cycle consists of several Clock cycles (T-...


43

The Z80 has an address space of 64KB. That means it can perform 8 bit reads or writes to 65,536 distinct locations as specified by the 16 address pins on the CPU. As far as the Z80 is concerned that's all it knows about. Now it's up to the system designer to decide which of those locations lead to RAM, which lead to ROM, which might lead to memory mapped ...


39

In the case of the Z80, the ALU is only 4 bits wide. That's no problem, since the internals of the CPU are controlled by a program internal to the processor, called the microprogram (or microcode), which is responsible for piping data around in the necessary way to execute some instruction. So if the Z80 gets an instruction like ADD HL, BC, the microprogram ...


38

They both shared the same memory so it didn't really forward instructions. The Z80 card stopped the 6502 running using the DMA signals and the system swapped between the two by writing to $CN00 where N is the slot number. Since the memory was shared the Z80 stuffed some values (A,X,Y,P) into the 6502 zero page ($F045 and up from the Z80 side) stored the ...


37

Little is known about how these computers and chips were made, because their development was top secret in the Soviet Union. As far as I know, Soviet Western-compatible ICs were made by copying masks used in fabrication or by buying manufactured products under fake identities and smuggling them back into Socialist countries where they were reverse-...


37

One reason you didn't see many Z80B machines is that not much was available in the way of affordable support chips for it. For example, look at the advert you cite: it has prices for PIO, CTC, DMA, and SIO chips to work with either Z80 or Z80A, but for the Z80B there are no DMA or SIO chips listed, and the PIO and CTC chips are much more expensive. You ...


36

Simple answers one easily gets to this question are The Z80 Sucks and C Sucks - depending on the side someone is on. While they are of course, untrue (*1), there are real issues. A major argument for both sides is that C is at core tied to a PDP-11(ish) CPU architecture and the Z80 isn't one. The Z80 is a rather special CPU, created with a focus on maxing ...


36

How did 8 bit processors such as the Z80 and 8080 perform 16 bit arithmetic? Same way one adds multiple digit numbers on paper. One digit (-pair) at a time and iterating over all digits while incooperating any carry. With(in) a CPU the chunks are ALU sized units like 4/8/16 or 32 bit. As with paper based addition this method can be used for numbers of ...


34

The definition of "instruction" and "OP code" (aka operation code) is a bit fuzzy because it depends on how humans view the CPU. So the designers and their marketing department mostly get to pick the numbers. Operation code is the easier of the two: it is the number of different valid instruction byte sequences, excluding those parts of the instruction that ...


34

The key to efficient programming on Z80 is to use registers as much as possible. I can easily believe that designers of Z80 intended the use of the alternative set of registers as an efficient way of context switching. However, the context switching does not tend to happen often enough to use the alternative set of registers only for that; the gains are ...


33

It seems to be pretty much accepted wisdom that the Soviets completely cloned the Western chips and did not simply develop reimplementations of the same instruction sets. Since at the time it was pretty important to have the impression of having own developments, the copying was obviously not admitted publicly so not much is known about how exactly the ...


33

An instruction set can be considered as a Huffman coding of an idealised instruction stream. So the question is really asking which CPUs have a good balance of short encodings for common tasks to longer encodings for rare tasks. However, it is not sufficient to just look at the encoding of individual instructions because a RISC instruction generally does ...


33

The intermediate carry flag, or "adjust flag", or half-carry flag is used to facilitate binary-coded decimal (BCD) arithmetic, where each decimal digit of a number is represented as a nibble (a group of 4 bits). The range of valid values for each nibble is 0 to 9 (0000 to 1001). If, after an arithmetic operation, the result contains a "non-...


31

No, they cannot. They share both the data and the address bus of the C128, so they can only run exclusively at any one point in time. The address bus is apparently directly connected, the data bus of the Z80 through a set of latches to the data bus of the rest of the system. In CP/M mode, the 8502 is handling keyboard, screen and printer and serial ...


31

If we consider only real Z80 (i.e. no emulation and no FPGA), probably the fastest Z80 compatible CPU is eZ80 (runs at 50 MHz, but has 3-stage pipeline, so in theory it could reach 3× the speed of Z80 at the same frequency). This hobbyist project describes eZ80 board and CP/M running natively on in, author says "The system runs Z80 code on average 30 times ...


31

Both processors are cacheless. So the process is fetch instruction, decode instruction, execute instruction, forget what you saw. That provides a first line of comparison. The Z80's fastest memory fetch — the first half of an operation fetch — takes two cycles. That's always paired with another two cycles for refresh though, so the shortest instructions are ...


29

In some cases undocumented instructions may be useful as shortcuts to accomplish tasks that are "difficult" to achieve with the official instructions. Going with the Z80, it is common practice amongst developers to make use of the undocumented instructions that allow to access index registers IX and IY as pairs of 8-bit registers (so IXh, IXl, IYh, IYl). ...


29

The MK 3880 Mostek CPU Technical manual (it's the Z80 implementation from Mostek) has a section called "Hardware implementation examples" which may help you. Besides, the Thomas Scherrer Z80-Family Official Support Page has a section devoted to circuit schematics based upon the Z80 processor. If you are in Facebook, there is a group devoted to share ...


27

There's no real optimisation — LDIR (or indeed LDDR, which goes downward instead of upwards) is the complete inner loop. It will always load from HL, store to DE, increment both and decrement BC. Then if BC is non-zero it will repeat. Annoyingly it will repeat exactly by just decrementing the PC by 2. So it'll read the full instruction again. Which means ...


27

Yes, it starts from Zero - like the Intel 8080, the Z80 descends from. Excerpt from Zilog's March 1978 Product Specification (datasheet), page 2, Pin Description, here the /RESET signal (emphasis mine): Input, active low. RESET initializes the CPU as follows: reset interrupt enable flip-flop, clear PC and registers I and R and set interrupt to 8080A ...


26

... a scaled-down, cost-reduced, clone of the Intel 8080. The Z80 had a massively extended instruction set, featured more addressing modes and had more registers than the 8080. It also had a built-in DRAM refreshing logic. ... and it was more expensive than the 8080! This is the opposite of "cost-reduced". It only used a 4-bit ALU. I assume this would ...


25

The M1 line literally means machine cycle 1 — and you're right about timing; the instruction fetch part of an M1 cycle is only two clock cycles long and will sample the data lines in the first clock cycle that it finds WAIT not asserted in, whereas a normal read is three clock cycles long and will sample the data lines in the clock cycle immediately after ...


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