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10

The TRS-80 series is Z80 based, and Z80 uses, like all 8080 offspring (*1,3) a separate address space for I/O. It allows easy decoding for I/O. Thus memory address 0000h is different from I/O address 00h. On logical (program) level, access to either address space is selected by the instructions used. Memory instructions always access memory address space ...


7

The main TRS-80 line (Model I, III and 4) had several third party Z-80 accelerator boards. The Archbold board could bring the Model I up to 5.3 MHz from 1.77 MHz. The Holmes Sprinter boosted the Model I up to 5.32 MHz. It came in a Model III version to boost it from 2.027 MHz to 5.07 MHz. The Model 4 had several speedup board options. Incidentally, the ...


6

For the Amstrad PCW, there was the Sprinter card - containing an 8MHz Z80 CPU that replaced the 4MHz original, a memory expansion, and cache RAM so that the processor wasn't restricted to the speed of motherboard memory. PCWs were largely used for word processing and DTP rather than gaming; in these applications it's useful to have more memory and a faster ...


6

Yes, accelerators did exist - but they were usually niche products, or handled completely differently (see below). It's more of a market-driven issue than ability to speed up. Home computers never really had a big need for speed improvement. After all, any speed up would not only break games, but also be rather expensive, as the host system wasn't really ...


10

I'm not familiar with the C64, and didn't do much with the Apple ][ back in the day, but I did spend a lot of time under the hood of my TRS-80. There wasn't a lot of room for plugin accelerators in the TRS-80 Model I. I did put in a CP/M daughtercard, which remapped system memory to get ROM out of the low address space, but didn't replace the processor. ...


6

In this document there is a mentioning of half a million dollars spent for designing the Z80.


7

So I'm assuming to get those bits from the interrupting device the Z80 needs to execute an IN A,(*) instruction (or other input instruction)? [I assume the IN instruction mentioned is just meant as a place holder for an internal way to fetch the vector] There is a special bus transaction to fetch the vector, the Interrupt Response Cycle, as shown here from ...


6

No it does not execute any separate instruction to fetch the interrupt vector, but the CPU generates a special interrupt acknowledge bus cycle and during this cycle the interrupting device places the interrupt vector on data bus. That is then combined with I register to use it as an address from where to fetch the address to jump to.


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