Timeline for What "unusual" syntax assembly languages are/were there?
Current License: CC BY-SA 4.0
21 events
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| Apr 24 at 16:37 | history | edited | dirkt | CC BY-SA 4.0 |
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| Apr 24 at 10:20 | comment | added | ninjalj | See also github.com/larsbrinkhoff/vt52-simulator/tree/master/lst for some examples of VT50/VT52 assembly/disassembly. | |
| Apr 24 at 10:13 | comment | added | ninjalj | The VT52 is similar to that PDP-8 operation: instructions are 8 bits, bits are named ABCDEFGH, if A=0, BCD select from 8 instruction groups, and each of E, F, G, H select an action, with an additional action for EFGH all zero. vt100.net/docs/vt52-mm/chapter4.html#S4.3.1.3 | |
| Apr 24, 2020 at 2:12 | vote | accept | dave | ||
| Apr 24, 2020 at 2:11 | comment | added | dave | I'm not entirely convinced that the PDP-8 counts as weird. It's fairly conventional syntax except for the existence of the OPR instructions. But the CDC 6600's total confusion of operand and opcode makes up for it - now that is weird! | |
| Apr 22, 2020 at 4:45 | comment | added | dirkt | @another-dave Yes. | |
| Apr 21, 2020 at 23:06 | comment | added | dave | If I recall correctly, PAL-8 syntax is just to 'or' together expressions it finds on the same line. | |
| Apr 21, 2020 at 4:20 | comment | added | dirkt |
@Zeus You can write them in any order in assembly. The order of "execution" is always the same, and determined by the way the functional blocks are arranged in the hardware. So you can both write CLA IAC and IAC CLA, but the accumulator always gets cleared first, because that's just a pulldown/and gate where the signal exits the "old" accumulator.
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| Apr 21, 2020 at 2:08 | comment | added | Zeus |
What determines the order of the combined operations in PDP-8? I.e. why 7201 is CLA IAC and not IAC CLA?
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| Apr 20, 2020 at 15:10 | comment | added | Peter Smith |
The Harris RTX2000 (real time processor as it was called as I recall) was designed to directly implement FORTH. I remember going to a Harris seminar in the mid - late 80s where it was introduced. Interesting page at users.ece.cmu.edu/~koopman/stack_computers/sec4_5.html
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| Apr 19, 2020 at 4:07 | comment | added | dirkt |
@another-dave Right. And not only is the 1 an operand designator, you can also have commands like SA1 A2 + B3 and SB1 A2 + B3 where A1 means register A1, and B1 register B1, just as X1 means register X1 in BX1; and S means "set to".
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| Apr 18, 2020 at 22:47 | comment | added | dave |
OK, the CDC 6000 assembler (COMPASS) is authentically weird. In BX1 X2 * X3, there are multiple opcodes with the same BX1 mnemonic, the 1 is actual an operand designator, and the * is part of the opcode. Right?
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| Apr 18, 2020 at 20:30 | history | edited | dirkt | CC BY-SA 4.0 |
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| Apr 18, 2020 at 19:12 | comment | added | Jens |
RAR appears twice with different opcodes. Typo?
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| Apr 18, 2020 at 15:16 | comment | added | dirkt | @another-dave Yes, it's a single instruction, like the other examples. | |
| Apr 18, 2020 at 14:13 | comment | added | dave |
For the CDC 6000 example, is BX1 X2 * X3 still a single machine instruction?
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| Apr 18, 2020 at 10:47 | comment | added | Grabul | Maybe SHARC DSPs assembly, using infix notation and showing parallel execution of load/store, ALU... | |
| Apr 18, 2020 at 7:49 | comment | added | matja | I was going to mention Forth CPUs, the example I was thinking of was the GreenArrays GA144 - which will seem familiar to those who have played TIS-100 :) . Example MD5 implementation on a GA144 : greenarraychips.com/home/documents/greg/AN001-141023-MD5.pdf | |
| Apr 18, 2020 at 6:47 | comment | added | Michael Karcher | Example 1 sounds quite similar to the HP 1000 series CPU. It's assembly language contained two "groups" called "alter / skip" and "shift / rotate", in which instructions could be combined by ORing them. | |
| Apr 18, 2020 at 3:49 | history | edited | dirkt | CC BY-SA 4.0 |
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| Apr 18, 2020 at 3:09 | history | answered | dirkt | CC BY-SA 4.0 |