I have solved a similar problem when reworking my 8085-based OMEN Alpha computer for the Z80 CPU. The memory part is really simple:

You have two memories, 32k each, and you should map the EEPROM from 0000h, RAM from 8000h. I use common data and address bus, as well as the control bus (/RD and /WR). The only memory-specific signals are /RAMCS and /ROMCS. They are generated by 74HCT00 chip this way:

As you can see, all you need is the A15 (the highest) address signal, gated by /MREQ signal.

/ROMCS is active(=0) when MREQ is active and A15=0, /RAMCS is active when MREQ is active and A15=1

I have solved a similar problem when reworking my 8085-based OMEN Alpha computer for the Z80 CPU. The memory part is really simple:

You have two memories, 32k each, and you should map the EEPROM from 0000h, RAM from 8000h. I use common data and address bus, as well as the control bus (/RD and /WR). The only memory-specific signals are /RAMCS and /ROMCS. They are generated by 74HCT00 chip this way:

As you can see, all you need is the A15 (the highest) address signal, gated by /MREQ signal.

/ROMCS is active(=0) when /MREQ is active and A15=0, /RAMCS is active when /MREQ is active and A15=1