Timeline for How do multi-byte instructions work?
Current License: CC BY-SA 4.0
15 events
| when toggle format | what | by | license | comment | |
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| May 29, 2020 at 6:57 | comment | added | Patrick Schlüter | Watch Ben Eaters excellent 8 bit cpu on a breadboard series of videos. youtube.com/… | |
| May 28, 2020 at 20:53 | comment | added | user3528438 | A third solution is to mv address into a register and ld/st using a register operand (RISC-style). You need to support that anyway because not all addresses are known at compile time. Also it's not multi-byte instructions are difficult, but variable length instructions. That's why new ISAs all tries to avoid it by doing it the other way: fetching a word a time and decode it into one(normal format) or two operations (compressed format). | |
| May 28, 2020 at 17:54 | vote | accept | Nip Dip | ||
| May 28, 2020 at 15:58 | answer | added | Raffzahn | timeline score: 4 | |
| May 28, 2020 at 15:44 | comment | added | Raffzahn | @Wilson True. But his problem isn't how a specific CPU works, but the general working ... and to be honest, I have an ida were he's stuck, but that's again a generic design issue, nothing specific RC. | |
| May 28, 2020 at 15:42 | comment | added | Omar and Lorraine | @Raffzahn Yes. But it could be made on-topic if ask about a specific implementation. | |
| May 28, 2020 at 15:41 | comment | added | Raffzahn | I'm inclined to vote for colure, as this is not an RC specific question, but a general CS/EE one: How to design a (word) size CPU wit multi word instructions. | |
| May 28, 2020 at 15:01 | comment | added | Nip Dip | But it is fundamentally more difficult. The CPU has to do another fetch cycle, which means resetting the control unit while storing the opcode an a register and then after that fetching the operand. Then the CPU must have a machine that knows when the fetching is going to stop and if this is sounding confusing then it is. A single byte instruction only requires you to fetch once every time, not some variable amount. | |
| May 28, 2020 at 13:11 | comment | added | Solomon Slow | I'm guessing that if you think decoding and executing a multi-word instruction is fundamentally more difficult than decoding and executing a single-word instruction, then you probably haven't given a lot of thought to the sequences of things that a CPU must do to decode and execute many of the single-word ones. For the broadest of broad strokes, you might want to Google for information about "Sequential logic circuits." | |
| May 28, 2020 at 8:16 | answer | added | Omar and Lorraine | timeline score: 6 | |
| May 28, 2020 at 7:01 | answer | added | ufok | timeline score: 2 | |
| May 28, 2020 at 6:45 | history | edited | hippietrail |
cpu tag
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| S May 28, 2020 at 5:54 | history | suggested | TonyM | CC BY-SA 4.0 |
Split up single-paragraph question.
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| May 28, 2020 at 5:36 | review | Suggested edits | |||
| S May 28, 2020 at 5:54 | |||||
| May 28, 2020 at 4:55 | history | asked | Nip Dip | CC BY-SA 4.0 |