But in any case, doesn't the Altair front panel depend on the ability to do exactly what is described, tri-state the CPU in order to take over as a DMA device? Would that be a significant obstacle to building such a system around the 6502 (at least without having to provide extra logic which would tend to negate the cost advantage of the CPU itself)?

Depends on what you want to reach and how.

For simply single stepping, i.e. let the CPU execute a single instruction per step, the classic solution is using the NMI and handle everything else in software, which is in line with the basic 6502 idea of do as much in software. This method was for example used with the KIM. When the SST switch is set, every instruction outside the KIM ROM (*1) fetched (marked by SYNC) will issue a NMI, which is served by the ROM, giving control back to the monitor, allowing any operation to examine/change memory, I/O and as well registers (*2), something not possible by taking over the bus.

Singe cycling, i.e. let the CPU execute one and exactly one clock cycle per step, needs to be done in hardware. Here it's simply about pulling RDY. This works because every cycle of a 6502 is a memory cycle, so pulling RDY will extend that memory access for as many cycles as RDY is active.

While the basic logic is rather simple, it gets a bit more sophisticated when combining functions. Still, the whole circuitry for single stepping cycles and instructions needs just 6 TTL and fits on a single page of the Hardware Manual (Figure 3.1 on p.125 of the January 1976 second edition - aka white books). [*2]

Of course this only lets one static examine bus state and all signals. To be able to read/write memory independent of the CPU, as set of tristate buffers and/or muxes would be needed to take over the bus while the CPU is halted.

Over all hardware effort would be comparable with Altairs front panel.

*1 - That is only the KIM ROM (6530-002 at $1C000), not the cassette extension (6530-003 at $1800).

*2 - Looked it up on paper, so no image ... I'll try to get one later.

But in any case, doesn't the Altair front panel depend on the ability to do exactly what is described, tri-state the CPU in order to take over as a DMA device? Would that be a significant obstacle to building such a system around the 6502 (at least without having to provide extra logic which would tend to negate the cost advantage of the CPU itself)?

Depends on what you want to reach and how.

For simply single stepping, i.e. let the CPU execute a single instruction per step, the classic solution is using the NMI and handle everything else in software, which is in line with the basic 6502 idea of do as much in software. This method was for example used with the KIM. When the SST switch is set, every instruction outside the KIM ROM (*1) fetched (marked by SYNC) will issue a NMI, which is served by the ROM, giving control back to the monitor, allowing any operation to examine/change memory, I/O and as well registers (*2), something not possible by taking over the bus.

Singe cycling, i.e. let the CPU execute one and exactly one clock cycle per step, needs to be done in hardware. Here it's simply about pulling RDY. This works because every cycle of a 6502 is a memory cycle, so pulling RDY will extend that memory access for as many cycles as RDY is active.

While the basic logic is rather simple, it gets a bit more sophisticated when combining functions. Still, the whole circuitry for single stepping cycles and instructions needs just 6 TTL and fits on a single page of the Hardware Manual :

(Figure 3.1 on p.125 of the January 1976 second edition)

Of course this only lets one static examine bus state and all signals. To be able to read/write memory independent of the CPU, as set of tristate buffers and/or muxes would be needed to take over the bus while the CPU is halted. Plus the usual bunch of switches and LED ofc.

Over all hardware effort would be comparable with Altairs front panel.

*1 - That is only the KIM ROM (6530-002 at $1C000), not the cassette extension (6530-003 at $1800).