From the Apple IIgs Hardware Reference, Second Edition, page 23pages 22-24:
Figure 2-6 - Speed register at SC036
Table 2-2 - Bits set in the Speed register
[...]
Bits 0-3†
Value 1
Description Disk II motor-on address detectors: To retain Apple II peripheral compatibility, the motor-on detectors change the system speed to 1.024 MHz whenever a Disk II motor-on address is detected.‡ When the disk motor-off address is accessed, the system speed increases, to 2.8 MHz again. For example, when bit 1 is 1, the FPI switches to 1.024 MHz when address $C0D9 is accessed, and returns to 2.8 MHz following a $C0D8 access. (See list of addresses below.)
Value 0
When this bit is 0, the Disk II motor detectors are turned off.
Bits 0 through 3 detect the following addresses:
Bit Slot Motor on Motor off 0 4 $C0C9 $C0C8 1 5 $C0D9 $C0D8 2 6 $C0E9 $C0E8 3 7 $C0F9 $C0F8* Drives designed for the Apple IIGS system should use the speed bit (Speed register bit 7) to change the processor speed when accessing disks, rather than the disk motor-on detectors (speed register bits 0 through 3). By using bit 7 you access drives in slots other than 4 through 7 by changing the system speed manually. Be aware that central processor speed changes for drive compatibility may affect application program timing; avoid using the motor addresses unless they are used in a fashion consistent with the drive's central processor speed requirements.
† For compatibility with future Apple products, use firmware calls only to manipulate bits 0 to 3 of the Speed register.
‡ Drives designed for previous Apple II computers will function as Apple IIGS peripherals only if the system speed is changed to 1.024 MHz before disk access is attempted.
Luckily we can use MAME to see how it's set by running it with a Disk II card:
mame apple2gsr1 -sl6 diskiing -debug
Then setting watch points for $C600-$C6FF and $C036:
wp c600,100,rw
wp c036,1,rw
Here's the output.
MAME debugger version 0.229 (mame0229)
Currently targeting apple2gsr1 (Apple IIgs (ROM01))
>wp c600,100,rw
Watchpoint 1 set
>wp c036,1,rw
Watchpoint 2 set
Stopped at watchpoint 2 reading 80 from 0000C036 (PC=F8A6)
Stopped at watchpoint 2 writing 80 to 0000C036 (PC=F8AC)
Stopped at watchpoint 1 reading 03 from 0000C605 (PC=FFFA07)
Stopped at watchpoint 1 reading 00 from 0000C603 (PC=FFFA07)
Stopped at watchpoint 1 reading 20 from 0000C601 (PC=FFFA07)
Stopped at watchpoint 1 reading 00 from 0000C6FF (PC=FFFA12)
Stopped at watchpoint 2 writing 84 to 0000C036 (PC=FFFFE2)
Stopped at watchpoint 2 writing 80 to 0000C036 (PC=F8B4)
...
Stopped at watchpoint 2 reading 80 from 0000C036 (PC=F8A6)
Stopped at watchpoint 2 writing 80 to 0000C036 (PC=F8AC)
Stopped at watchpoint 1 reading 00 from 0000C6FB (PC=FFA268)
Stopped at watchpoint 2 reading 80 from 0000C036 (PC=FF7082)
Stopped at watchpoint 2 writing 80 to 0000C036 (PC=F8B4)
Stopped at watchpoint 1 reading 03 from 0000C605 (PC=FA07)
Stopped at watchpoint 1 reading 00 from 0000C603 (PC=FA07)
Stopped at watchpoint 1 reading 20 from 0000C601 (PC=FA07)
Stopped at watchpoint 1 reading 00 from 0000C6FF (PC=FA12)
Stopped at watchpoint 2 writing 84 to 0000C036 (PC=FFE2)
Stopped at watchpoint 1 reading 03 from 0000C605 (PC=FACB)
Stopped at watchpoint 1 reading 00 from 0000C603 (PC=FACB)
Stopped at watchpoint 1 reading 20 from 0000C601 (PC=FACB)
Stopped at watchpoint 1 reading A2 from 0000C600 (PC=C601)
