Timeline for Why does the 6502 JSR instruction only increment the return address by 2 bytes?
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| Jul 4, 2023 at 17:12 | comment | added | Raffzahn | @supercat The address is handled during the first half while the fetch i during the second. The way 6500 pipelining always hasworked. | |
| Jul 4, 2023 at 16:13 | comment | added | supercat | I don't think I'd describe the last step as "interleaved" as "in preparation for", on the basis that the next instruction can't really start executing until it's fetched. Also, does PC get loaded with ADH:ADL, or is a byte fetched from ADH:ADL while PC gets loaded with (ADH:ADL)+1? | |
| Jul 4, 2023 at 14:31 | history | edited | Raffzahn | CC BY-SA 4.0 |
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| Jul 4, 2023 at 13:58 | history | edited | paxdiablo | CC BY-SA 4.0 |
Grammar and spelling improvements.
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| Apr 10, 2021 at 21:35 | comment | added | supercat | ...it could load the PC with the fetched PCH at that time, without having performed any read cycles between the time the new PCH was loaded and the time it's copied to the register. An interesting aspect of this approach is that it might have been possible to shave a cycle off the cost of any JSR that isn't immediately followed by a page boundary, since writing the PCH value for the third byte of the instruction would eliminate the need to write the PCH value for the following instruction. | |
| Apr 10, 2021 at 21:32 | comment | added | supercat | From what I can tell, in machines of the 6502 era, the main cost of registers was the wiring to get data into and out of them. Inserting an extra 8-bit latch on the input to the upper program counter byte, between the bus that fed it and the register itself, would seem like it would not have been difficult, especially if a dynamic latch would have sufficed (if the CPU wrote the high byte of the PC of the third byte of the instruction on the cycle after it fetched that byte, then wrote the high byte of the PC of the instruction after that to the same address, ... | |
| Apr 10, 2021 at 18:04 | comment | added | Raffzahn | @JeroenJacobs Well, an 8086 got more than 10 times the gate count of a 6502. Also, more important here, it handles data as 16 bit chunks, so no need to juggle with two bytes. In addition this is handled by special circuitry of the BIU anyway. It's predecessor, the 8080/Z80 line does in fact have a hidden register pair (WZ) to hold the read address thur all of this. The 6502 simply improved thereon. | |
| Apr 10, 2021 at 17:29 | vote | accept | Jeroen Jacobs | ||
| Apr 10, 2021 at 17:29 | comment | added | Jeroen Jacobs | Thanks for this interesting explanation. The reason I find it complex and not very "logical", is because the return address on the stack does not point to the next instruction after return, but to the last byte of the JSR itself. This just feels totally weird to me (compared to x86 architecture where the return address pushed by CALL is the address of the actual next instruction, RET just pops and jumps) :) I'm not a hardware engineer, so I don't know the difficulties or costs of creating a CPU (certainly not back in those days). | |
| Apr 10, 2021 at 17:01 | history | edited | Raffzahn | CC BY-SA 4.0 |
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| Apr 10, 2021 at 16:55 | history | edited | Raffzahn | CC BY-SA 4.0 |
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| Apr 10, 2021 at 16:42 | history | edited | Raffzahn | CC BY-SA 4.0 |
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| Apr 10, 2021 at 16:36 | comment | added | Raffzahn | @WayneConrad ROTFL ... yeah, then again, not wrong either. It's a RTFM story :)) | |
| Apr 10, 2021 at 16:34 | history | edited | Raffzahn | CC BY-SA 4.0 |
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| Apr 10, 2021 at 16:34 | comment | added | Wayne Conrad | Typo in the footnote? | |
| Apr 10, 2021 at 16:29 | history | edited | Raffzahn | CC BY-SA 4.0 |
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| Apr 10, 2021 at 16:21 | history | answered | Raffzahn | CC BY-SA 4.0 |