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May 25, 2021 at 14:21 vote accept mdm
S May 25, 2021 at 13:59 history suggested Peter Mortensen CC BY-SA 4.0
Copy edited (e.g. ref. <https://en.wikipedia.org/wiki/Gate_array> - if it is a specific one, it should be specified (but it is still not a proper noun)). Removed historical information (that is what the revision history is for) - the question should be as if it was written right now.
May 25, 2021 at 13:35 review Suggested edits
S May 25, 2021 at 13:59
May 24, 2021 at 23:13 answer added Tommy timeline score: 9
May 24, 2021 at 21:11 history became hot network question
May 24, 2021 at 19:14 answer added lvd timeline score: 5
May 24, 2021 at 14:34 answer added Raffzahn timeline score: 9
May 24, 2021 at 14:33 history edited mdm CC BY-SA 4.0
Add reference link
May 24, 2021 at 14:16 comment added Brian H Agree with Tommy in that it's generally the peripheral that controls an interrupt line, not the CPU. i.e IRQ is an input.
May 24, 2021 at 14:11 comment added Tommy I had the belief that the CPC holds the interrupt line until it sees an interrupt acknowledgement cycle, but cannot find a reference. I'll see whether I can dig anything out.
May 24, 2021 at 13:08 history asked mdm CC BY-SA 4.0