I worked with this machine for many years, mostly while employed at Digital Equipment Corporaion. The code in our library for multiple-precision subtraction was:

        CLA             ; not required if previous code always leaves AC==0
        TAD  B
        CLL CMA CML IAC ; form 13-bit negative with no previous borrow
        TAD  A          ; generates 0 for borrow, 1 for no borrow
        DCA  C
        RAL             ; propagate "complemented" borrow
        TAD  B+1        ; add previous stage borrow before forming negative
        CMA CML IAC     ; form 13-bit negative
        TAD  A+1        ; generates 0 for borrow, 1 for no borrow
        DCA  C+1
        RAL             ; propagate "complemented" borrow
        TAD  B+2        ; add previous stage borrow before forming negative
        CMA CML IAC     ; form 13-bit negative
        TAD  A+2
        DCA  C+2        ; et.seq. for further precision
        ; for unsigned arguments, the link now indicates a negative result

The static load is an irreducable 5 instructions per additional word of precision. The dynamic load is 8 to 11 cycles per word of precision, depending on indirection.

The PDP-8 programmers I worked with at DEC felt this arrangement of operations was the most easily proved correct. Some DECUS contributors may have had other opinions.

I worked with this machine for many years, mostly while employed at Digital Equipment Corporaion. The code in our library for multiple-precision subtraction was:

        CLA             ; not required if previous code always leaves AC==0
        TAD  B
        CLL CMA CML IAC ; form 13-bit negative with no previous borrow
        TAD  A          ; sets link to 0 for borrow, 1 for no borrow
        DCA  C
        RAL             ; propagate "complemented" borrow
        TAD  B+1        ; add previous stage borrow before forming negative
        CMA CML IAC     ; form 13-bit negative
        TAD  A+1        ; sets link to 0 for borrow, 1 for no borrow
        DCA  C+1
        RAL             ; propagate "complemented" borrow
        TAD  B+2        ; add previous stage borrow before forming negative
        CMA CML IAC     ; form 13-bit negative
        TAD  A+2
        DCA  C+2        ; et.seq. for further precision
        ; for unsigned arguments, the link now indicates a negative result

The static load is an irreducable 5 instructions per additional word of precision. The dynamic load is 8 to 11 cycles per word of precision, depending on indirection.

The PDP-8 programmers I worked with at DEC felt this arrangement of operations was the most easily proved correct. Some DECUS contributors may have had other opinions.