Timeline for Why does the Commodore C128 perform poorly when running CP/M?
Current License: CC BY-SA 3.0
19 events
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| Jun 15 at 18:48 | comment | added | supercat | @MarkReed: I don't know enough about the 8563's internals to know what parts were designed well or badly, but the general design philosophy is consistent with that of popular TI video chips that were use successfully in MSX machines, but likely using a higher memory bandwith to handle 80 columns with text and attributes. | |
| Oct 27, 2021 at 19:18 | comment | added | Martijn | Regarding "display bottleneck", for completeness sake: the code Von Erwine made doesn't operate as slow as suggested here. In fact the largest overhead is coming from the CPM3 'reference design' for display output. The actual 80col output is programmed directly from Z80 to VDC. The Z80 works hard to achieve the emulation for ADM31 ESC-codes, then calls the 80column routines in the Z80-boot-rom. Point is: no processor switches are involved in 80 or 40 char output. | |
| Nov 27, 2020 at 21:16 | comment | added | Mark Reed | I'm not quite convinced that the 8563 isn't a poor design; at the very least, given how long it took to get to a stable state, I have to wonder if it wasn't perhaps over-engineered. And the lack of interrupt-generation capability seems like an odd oversight. But it was also adapted from a completely different original target chipset, and the two-port indirect-access paradigm no doubt makes more sense if you're using a Z8000 without memory-mapped I/O. | |
| Mar 9, 2017 at 0:10 | comment | added | RichF | @supercat It may have, not sure. Sounds like a reasonable substitute since device-independent CP/M had no purpose for the C= key. I suspect most users would just use the SHFT LOCK key and not worry about the difference between CAPS and SHFT LOCK. | |
| Mar 9, 2017 at 0:01 | comment | added | supercat | @RichF: That reminds me... didn't CP/M ignore the caps-lock key and use the C= key as a toggle for that purpose? | |
| Mar 8, 2017 at 23:53 | comment | added | RichF | @supercat No "need". The Z80A can talk to both the 8583 and the VIC to control either the 80-col or 40-col screens. Both if you want. AFAIK, the problem with CP/M BIOS was that during development, the 8563s were very unreliable and "fixes" kept breaking other things. Their CP/M guy tried to use the 8563 directly, but in the end, the decision was made to kludge CP/M, having it call the 8502 BIOS code, which at some point the C128 folks knew would have to become rock solid. As far as I know, the only I/O value not available to the Z80 is the value of the CAPS LOCK key, fed directly to the 8502. | |
| Mar 8, 2017 at 23:24 | comment | added | supercat |
Is there any actual need to use the 8502 for screen updates? My recollection from back in the day is that I was able to change the screen color from within Z80 code by using the Z80's I/O instructions (while the instruction was called OUT (C),A", it actually put BC onto the address bus, and 0xD021 worked for the display).
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| Mar 7, 2017 at 1:02 | history | edited | RichF | CC BY-SA 3.0 |
more fixes
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| Mar 6, 2017 at 23:02 | history | edited | RichF | CC BY-SA 3.0 |
more on what the 8563 actually does
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| Mar 6, 2017 at 16:31 | history | edited | RichF | CC BY-SA 3.0 |
deleted 92 characters in body
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| Mar 6, 2017 at 16:26 | comment | added | RichF | I added a new section at the end, The Display Bottleneck. Since this was the "hardware answer", it seemed appropriate to show what was going on with the 8563 chip. I also replaced the keyboards picture with a clearer, expandable one, and made it clear that the overall C128 System Diagram is expandable as well. | |
| Mar 6, 2017 at 16:21 | history | edited | RichF | CC BY-SA 3.0 |
added Display Bottleneck section and replaced keyboards picture with better one
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| Mar 4, 2017 at 20:27 | comment | added | RichF | @BrianH assume writing a character to screen takes 4 msec, with 1 msec in z80 cp/m BDOS, 1 msec in z80 cp/m BIOS, and 2 msec in 8502 BIOS. (Numbers chosen for simplicity; I have no idea what ratios are, and it's likely faster overall than 4 msec.) Even if you could halve the time spent in 8502 BIOS, the operation would still take 3 msec. | |
| Mar 4, 2017 at 20:18 | comment | added | RichF | @BrianH I read the readme.txt file and looked at cx80.asm, but I could not get a feel on how it fits with the CP/M BIOS. I had assumed until you asked this that he was talking to the 8563 directly and avoiding the 8502 BIOS calls altogether. But if he is still making the calls via the 8502, having it be in 2 MHz would only help a little. Note that during I/O access, the system clock is forced to 1 MHz. The ratio of non-IO to I/O code in the 8502 video BIOS would determine how effective 2 MHz would be. In larger picture, you still have Z80 BDOS and BIOS overhead. | |
| Mar 4, 2017 at 17:09 | comment | added | Brian H | Have you looked at the CPMFAST distribution for the C128? If I understand the modifications, it runs the 8502 in 2MHz mode during its execution of CP/M BIOS calls. | |
| Mar 4, 2017 at 17:06 | comment | added | Brian H | I appreciate the diagram that shows how the pseudo-wait-state happens on the Z80A data bus access. A pictures is worth a 1000 words... | |
| Mar 4, 2017 at 16:04 | history | edited | RichF | CC BY-SA 3.0 |
more keyboard info
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| Mar 4, 2017 at 11:22 | history | edited | RichF | CC BY-SA 3.0 |
mentioned more on 8563 registers
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| Mar 4, 2017 at 3:36 | history | answered | RichF | CC BY-SA 3.0 |