Timeline for Why doesn't the NMOS 6502 have the illegal instruction, STA immediate?
Current License: CC BY-SA 4.0
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| Sep 30, 2022 at 15:45 | vote | accept | Omar and Lorraine | ||
| Sep 30, 2022 at 6:11 | history | edited | user3840170 | CC BY-SA 4.0 |
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| Sep 28, 2022 at 19:04 | history | edited | supercat | CC BY-SA 4.0 |
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| Sep 28, 2022 at 18:58 | comment | added | supercat | @Raffzahn: If the designers of the 6502 had thought store immediate would be useful, there are two approaches they could have taken to supporting it. Supporting two-cycle store-immediate instructions while satisfying timing constraints would likely have been possible but expensive. Supporting three-cycle store-immediate instructions would have been cheaper, but the time penalty would undermine the usefulness of those instructions. In neither approach would the benefit offered by the approach exceed the cost thereof. | |
| Sep 28, 2022 at 18:50 | comment | added | supercat | @benrg: The issue isn't that there's separate logic, but rather that the CPU's decision of what to do on the cycle following an opcode fetch must be made before the CPU can know what the opcode will be. The designers of the 6502 decided to use that cycle to perform a fetch of the byte following the opcode, on the basis that doing so would be useful most of the time, and would almost always be harmless even in cases where it isn't useful (it could cause problems if e.g. address $BFFF held an RTS and address $C000 was mapped to read-triggered I/O, but such issues would be rare). | |
| Sep 28, 2022 at 17:52 | comment | added | Raffzahn | @supercat you're trying to explain this by adding meta reasoning - something a CPU doesn't do. This may be used to explain why someone want to have that behaviour, but not why the CPU is working that way. | |
| Sep 28, 2022 at 17:16 | comment | added | benrg | I upvoted, but I found the answer pretty confusing. I didn't understand where the explanation was going until the first sentence of paragraph 3. I wonder if you could summarize at the top, perhaps along the lines of "there is separate instruction-fetching and data-access logic, and immediate operands are handled by the instruction-fetching logic, which only does reads"—assuming that is accurate. | |
| Sep 28, 2022 at 16:58 | comment | added | supercat | @MichaelGraf:" Thanks. Corrected. The key point is that by the time the 6502 could know that it should do a write on the second cycle to avoid having to do one later, the opportunity to do so without wasting a cycle would have passed. | |
| Sep 28, 2022 at 16:56 | history | edited | supercat | CC BY-SA 4.0 |
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| Sep 28, 2022 at 16:55 | comment | added | Michael Graf | Shouldn't it be "change that read to a write" in the second paragraph? | |
| Sep 28, 2022 at 16:19 | history | edited | supercat | CC BY-SA 4.0 |
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| Sep 28, 2022 at 16:13 | comment | added | supercat |
@Raffzahn: What do you mean "not including the reason"? In order for the 6502 to process STA #imm as a store, it would have to be able to select whether the second cycle is a read or write based upon the value that was read in the first cycle, but the 6502's circuitry will already be committed to performing a read on the second cycle before data from the first cycle is available.
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| Sep 28, 2022 at 16:06 | history | edited | supercat | CC BY-SA 4.0 |
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| Sep 28, 2022 at 14:41 | history | answered | supercat | CC BY-SA 4.0 |