Timeline for Why memory read (M2) cycle in Z80 is three T cycles and not two?
Current License: CC BY-SA 4.0
5 events
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| Dec 24, 2022 at 19:51 | comment | added | Tommy | @AlanCox I think we’re saying the same thing: that not having one sort of access be a third shorter than the rest is the objective. But maybe it’s poorly phrased, in terms of suggesting that making things regular is a goal in itself, rather than a consequence of another objective. | |
| Dec 23, 2022 at 18:13 | comment | added | Alan Cox | They generally don't stretch it to make it regular, they stretch it because at 3.5MHz or so the instruction fetch was a tiny bit too fast for the cheap RAM of the time. Stretching just that cycle reduced the memory wait hit a fair bit | |
| Dec 9, 2022 at 15:30 | comment | added | BipedalJoe | Great answer overall! Would not have thought of that myself. | |
| Dec 9, 2022 at 15:29 | comment | added | BipedalJoe | Thanks for answer. I corroborated what you said, that the RAM/component being addressed would be so slow that an extra cycle is required, "Way back when, memory/IO etc was slow, e.g. it could take 500ns (or more) from valid address/chip select to having valid read data from the memory chip - so adding a WAIT state (or 2 or ...) would give one extra clock (or more) for the data to be valid. " eevblog.com/forum/projects/…. This seems counter-intuitive to me because it seems like it would be faster, but I guess it is the case. | |
| Dec 9, 2022 at 13:54 | history | answered | Tommy | CC BY-SA 4.0 |