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(With paging disabled, physical address = linear address. Paging is disabled in real/unreal mode, and is optional in protected mode. Mandatory for long mode. With paging enabled, 32-bit or 64-bit linear addresses are virtual, translated to physical by the page tables, and in 486 and later, by the TLB which is an actual cache of page-table entries (PTEs).)

(With paging disabled, physical address = linear address. Paging is disabled in real/unreal mode, and is optional in protected mode. Mandatory for long mode. With paging enabled, 32-bit or 64-bit linear addresses are virtual, translated to physical by the page tables and the TLB which is an actual cache of page-table entries (PTEs).)

Many people call this a "descriptor cache", but it's not just a cache. It's guaranteed to keep its state, never reloading from a GDT entry that might have changed. Nothing ever invalidates it, only writes a new value. And its value doesn't always come from a descriptor.

Many people (including Intel's documentation) call this a "descriptor cache", but it's not just a cache. It's guaranteed to keep its state, never reloading from a GDT entry that might have changed. Nothing ever invalidates it, only writes a new value. And its value doesn't always come from a descriptor.

(With paging disabled, physical address = linear address. Paging is disabled in real/unreal mode, and is optional in protected mode. Mandatory for long mode. With paging enabled, 32-bit or 64-bit linear addresses are virtual, translated to physical by the page tables, and in 486 and later, by the TLB which is an actual cache of page-table entries (PTEs). Apparently 386 didn't have a TLB, so every memory access became 3 DRAM accesses when paging was enabled!)

(With paging disabled, physical address = linear address. Paging is disabled in real/unreal mode, and is optional in protected mode. Mandatory for long mode. With paging enabled, 32-bit or 64-bit linear addresses are virtual, translated to physical by the page tables, and in 486 and later, by the TLB which is an actual cache of page-table entries (PTEs).)