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clarified BPL vs BMI
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This seems to follow the explanation from page 8, except that it uses BMI (branch when N is set) instead of BPL (branch when N is NOT set), and the comment even indicates that it is waiting for bit 7 of DSP Data to be cleared, not set.

This seems to follow the explanation from page 8, except that it uses BMI instead of BPL, and the comment even indicates that it is waiting for bit 7 of DSP Data to be cleared, not set.

This seems to follow the explanation from page 8, except that it uses BMI (branch when N is set) instead of BPL (branch when N is NOT set), and the comment even indicates that it is waiting for bit 7 of DSP Data to be cleared, not set.

fixed typo
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It would seem that Woz was using b7 as a flag, outputting it high and waiting for the displydisplay hardware to clear the flag, indicating that the next character could be output. This makes me think that the Wozmon listing must be correct, and the description of the output logic and DSP Data address must be incorrect, but I have not been able to find confirmation of this.

It would seem that Woz was using b7 as a flag, outputting it high and waiting for the disply hardware to clear the flag, indicating that the next character could be output. This makes me think that the Wozmon listing must be correct, and the description of the output logic and DSP Data address must be incorrect, but I have not been able to find confirmation of this.

It would seem that Woz was using b7 as a flag, outputting it high and waiting for the display hardware to clear the flag, indicating that the next character could be output. This makes me think that the Wozmon listing must be correct, and the description of the output logic and DSP Data address must be incorrect, but I have not been able to find confirmation of this.

Fixed typos
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Greenonline
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DSP DATA D012

Lower seven bits are data output, high order bit is "display ready" input (1 equals ready, 0 equals busy)

So the output logic is: use BIT to check bit 7 of the value in the Display Data address (This is the PIA's PB7 line), and if that bit is 0 (BPL branches when flag N is not set), go back and read it again. Stay in this loop until the display is ready (bit 7 of DSP Data is 1, so BITBIT sets NN to 1, and BPLBPL does not branch), the proceed to push the byte to the DSP Data address.

DSP DATA D012

Lower seven bits are data output, high order bit is "display ready" input (1 equals ready, equals busy)

So the output logic is: use BIT to check bit 7 of the value in the Display Data address (This is the PIA's PB7 line), and if that bit is 0 (BPL branches when flag N is not set), go back and read it again. Stay in this loop until the display is ready (bit 7 of DSP Data is 1, so BIT sets N to 1, and BPL does not branch), the proceed to push the byte to the DSP Data address.

DSP DATA D012

Lower seven bits are data output, high order bit is "display ready" input (1 equals ready, 0 equals busy)

So the output logic is: use BIT to check bit 7 of the value in the Display Data address (This is the PIA's PB7 line), and if that bit is 0 (BPL branches when flag N is not set), go back and read it again. Stay in this loop until the display is ready (bit 7 of DSP Data is 1, so BIT sets N to 1, and BPL does not branch), the proceed to push the byte to the DSP Data address.

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