Synchronizers in any main data path costs lots of dual-rank registers, which have to be tightly characterized in circuit design and layout. This costs in die area.

Async design also makes testing of the prototype emulator and chips themselves vastly more difficult. Thus making hard-to-find bugs far more likely on the products aggressive design schedule.

Easiest way out was to run all the wide fast paths (CPU, memory, BLIT, NTSC video) off the same derived clock edges.

Synchronizers, which are required for reliability and signal integrity across any asynchronous clock domain crossings, in any main data path, costs lots of dual-rank registers, which have to be tightly characterized in circuit design and layout. This costs in die area.

Async design also makes testing of the prototype emulator and chips themselves vastly more difficult. Thus making hard-to-find bugs far more likely on any product with such an aggressive design schedule.

Easiest way out was to run all the wide fast paths (CPU, memory, BLIT, NTSC video) off the same derived clock edges.

Synchronizers in any main data path costs lots of dual-rank registers, which have to be tightly characterized in circuit design and layout. This costs in die area.

Async design also makes testing of the prototype emulator and chips themselves vastly more difficult. Thus making hard-to-find bugs far more likely on the products aggressive design schedule.

Easiest way out was to run all the wide fast paths (CPU, memory, BLIT, video) off the same derived clock edges.

Synchronizers in any main data path costs lots of dual-rank registers, which have to be tightly characterized in circuit design and layout. This costs in die area.

Async design also makes testing of the prototype emulator and chips themselves vastly more difficult. Thus making hard-to-find bugs far more likely on the products aggressive design schedule.

Easiest way out was to run all the wide fast paths (CPU, memory, BLIT, NTSC video) off the same derived clock edges.