Timeline for How fast is memcpy on the Z80?
Current License: CC BY-SA 3.0
11 events
| when toggle format | what | by | license | comment | |
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| Oct 7, 2017 at 14:06 | comment | added | Raffzahn | @rwallace I found a high quality scan of the Feb 1980 data sheet online: bitsavers.org/components/zilog/z80/… | |
| Oct 7, 2017 at 14:04 | comment | added | Raffzahn | @rwallace My gut says right after the CPU. But I can't proof that. I don't have realy old documentation at hand. But from whats on my desk, it's already listed in the 1981 databook and a February 1980 datasheet - as well as the 1981 application reference. Furthermore I got a Z80 Family data book with no date (listing the 8410) which I assume to be eventually before 1979, as it refers to the 1979 databook in future form. Ao I go with anywhere between 1976 and 1978. | |
| Oct 7, 2017 at 13:34 | comment | added | rwallace | @Raffzahn Do you know when the Z8410 was released? All I've been able to find on Google is that it was not later than 1983. | |
| Sep 16, 2017 at 18:26 | comment | added | supercat |
If interrupts including NMI can be disabled, it's possible to write code that outperforms LDIR by using a sequence of stack manipulations, pops, register swaps, and pushes. LDIR is a lot easier, though. I do find myself curious how hard it would have been to make the microcode loop when no interrupt happens.
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| S Sep 16, 2017 at 14:26 | history | suggested | CommunityBot | CC BY-SA 3.0 |
Fix DE/HL confusion and rationale for continuable semantics
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| Sep 16, 2017 at 14:23 | review | Suggested edits | |||
| S Sep 16, 2017 at 14:26 | |||||
| Sep 16, 2017 at 8:54 | comment | added | Raffzahn | Thats also the reason why (at least somewhat) professional sysems always include a Z80 DMA (8410). A 4MHz Z80 can transfers a bit less than 200 KiB/s (unrolling gives ~250 KiB/s), as only 4 of 21 (16) cycles are memory access (half of it being instruchtion (re)fetch) me while the Z80 DMA uses the full bandwith, offering up to 2 MiB/s - all cycles are now used for data transfer. Ofc, minus video cycles, if that unit is also accessing the RAM. | |
| Sep 16, 2017 at 8:34 | comment | added | Raffzahn | The 6502 uses only half of each cycle for memory access, which means that memory has to be twice as fast as teh clock rate would suggest. So a 1 MHz 6502 needs >2 MHz RAM (better than 500 ns), but uses only half the bandwith, leaving between each access enough time for another one to be used by video (or otherwise). The Z80 instead doesn't run with such a symetric access scheme offering bontifull time to insert 'hidden' video access. Here video needs to be priortized over CPU, claiming the RAM when needed, thus 'stealing' cycles. We're at the heart of the decade old 6502 MHz vs. Z80 MHz topic. | |
| Sep 16, 2017 at 4:07 | comment | added | rwallace | So 21 cycles per byte, or 16 if you trade space for speed? Okay, thanks! Slower RAM - I thought a 4 MHz Z80 could do the same as a 1 MHz 6502, access RAM using only half the RAM bandwidth so as to leave the other half for video, is that not the case? | |
| Sep 16, 2017 at 4:06 | vote | accept | rwallace | ||
| Sep 16, 2017 at 3:52 | history | answered | Tommy | CC BY-SA 3.0 |