Timeline for Why do C to Z80 compilers produce poor code?
Current License: CC BY-SA 3.0
14 events
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| Oct 18 at 17:18 | comment | added | Peter Green | "What do you consider LDRLS x,[r1,r0,LSL #2] then" that is base + shifted index. To me "base+index+offset" implies adding three numbers to get the address, arm can only add two (one of which can optionally be shifted). | |
| Nov 4, 2022 at 10:40 | comment | added | tofro | ... and that was wrong anyways. See my direct answer in the comment. | |
| Mar 31, 2018 at 9:40 | comment | added | JdeBP | Being RISC or not is beside the point. Lưu Vĩnh Phúc was asserting that ARM (which xe called out specifically) cannot use base+index+offset register addressing, contradicting where the answer said that "modern CPUs" (well, "most more modern CPUs") could. | |
| Mar 30, 2018 at 16:42 | comment | added | Peter Cordes |
@Raffzahn: exactly. ARM is not RISC, but it has the good kind of complexity, which is not too hard for CPU designers to implement and which lets you get a lot done with fewer instructions. They dropped some of it for AArch64, though; e.g. no longer spending 4 bits per insn to predicate every instruction on flags. And no longer exposing the program counter as one of the general-purpose registers. And replacing store/load-multiple with store/load pair (stp / ldp). So they kept the feature of having instructions that write two integer registers; x86 CPUs take 2 uops for those (e.g. mul)
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| Mar 30, 2018 at 12:35 | comment | added | Raffzahn | @PeterCordes Prety nice example when a dogma (RISC) collieds with reality - and reality wins ... except ofc, with the dogmas priests. | |
| Mar 30, 2018 at 3:28 | comment | added | Peter Cordes | Being a load-store architecture with fixed-width instructions is necessary but not sufficient to really be fully RISC. Not every non-x86 architecture is RISC. ARM definitely doesn't fall neatly into the CISC category either, but it's not RISC. DarkShikari (x264 lead developer for several years / asm expert) argues this pretty well: reddit.com/r/programming/comments/8j25z/…, saying "ARM was RISC... a long, long time ago." (but the ARM ISA has evolved and grown). | |
| Mar 30, 2018 at 3:22 | comment | added | Peter Cordes |
ARM is not really a RISC ISA. It's somewhat RISCy, or shares some of their features, like fixed-width instructions (except Thumb2...), but an ISA with an instruction that does anywhere from 1 to 16 loads or stores depending on bits in a bit-field in the instruction is not a RISC. (I'm talking about ARM's push {r4, r5, r6, ..., lr} aka STMDB and corresponding pop instruction. The load/store-multiple instructions are microcoded because they're too complex and do a variable amount of work.
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| Mar 29, 2018 at 8:55 | comment | added | phuclv | I'm not familiar with ARM ISA but Even though the ARM is a RISC architecture, it does not strictly follow the RISC principles as does the MIPS... In addition, it provides a large number of addressing modes and uses a somewhat complex instruction format | |
| Mar 29, 2018 at 5:14 | comment | added | tofro |
@LưuVĩnhPhúc What do you consider LDRLS x,[r1,r0,LSL #2] then (ARM)?
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| Mar 29, 2018 at 4:26 | comment | added | phuclv |
Most more modern CPUs can use base + index + offset register addressing I don't think so. That doesn't apply to modern architectures like ARM, MIPS, PowerPC, Sparc...
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| Mar 29, 2018 at 2:54 | comment | added | Rich | I did just that in a Z80 (Spectrum and others) game I wrote. The core gameplay was in assembler, stuff like the leaderboard and help logic was in C. | |
| Mar 28, 2018 at 19:43 | history | edited | tofro | CC BY-SA 3.0 |
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| Mar 28, 2018 at 17:47 | history | edited | tofro | CC BY-SA 3.0 |
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| Mar 28, 2018 at 16:51 | history | answered | tofro | CC BY-SA 3.0 |