Your question assumes that CPUs with more than 40 pins were a rarity in the 1970s, but this was common for early 16-bit CPUs. Both the TI TMS9900 and the Motorola 68000 had 16-bit external data busses, no multiplexing, and came in a 64-pin DIP package.

The thing that was common at this time was DIP packaging. And the number of pins on a DIP package was limited by simple geometry - a rectangular package needs a progressively longer lead from the corner pins to the semiconductor chip as the number of pins increases. This geometry constraint limited DIPs to 64-pins, practically. This limitation also helped drive the transition from rectangular DIP to the various square packaging that followed.

The Intel 8086 came in a 40-pin DIP and relied on multiplexing for its 16-bit data bus (shared with address lines). The WDC 65C816 used the same 40-pin DIP and multiplexing scheme. Neither of these 16-bit CPUs were particularly successful in these packages. The 65C816 was repackaged for the SNES as the CPU core in a QFP package. The 80286 was the successful 16-bit successor to the DIP 8086 (and 8088) in 1982, and by that time square packaging was replacing DIPs.

In short, the market did not want a 16-bit CPU in a 40-pin DIP package with external demux. Fortunately, DIP soon gave way to newer packaging geometries that supported far higher pin counts.

Your question assumes that CPUs with more than 40 pins were a rarity in the 1970s, but this was common for early 16-bit CPUs. Both the TI TMS9900 and the Motorola 68000 had 16-bit external data busses, no multiplexing, and came in a 64-pin DIP package.

The thing that was common at this time was DIP packaging. And the number of pins on a DIP package was limited by simple geometry - a rectangular package needs a progressively longer lead from the corner pins to the semiconductor chip as the number of pins increases. This geometry constraint limited DIPs to 64-pins, practically. This limitation also helped drive the transition from rectangular DIP to the various square packaging that followed.

The Intel 8086 came in a 40-pin DIP and relied on multiplexing for its 16-bit data bus (shared with address lines). The WDC 65C816 used the same 40-pin DIP and multiplexing scheme. Neither of these 16-bit CPUs were particularly successful in these packages. The 65C816 was repackaged for the SNES as the CPU core in a QFP package. The Intel 80286 was the more successful 16-bit successor to the DIP 8086 (and 8088) in 1982, and by that time square packaging was replacing DIPs.

In short, the market did not want a 16-bit CPU in a 40-pin DIP package with external demux. Fortunately, DIP soon gave way to newer packaging geometries that supported far higher pin counts.

Your question assumes that CPUs with more than 40 pins were a rarity in the 1970s, but this was common for early 16-bit CPUs. Both the TI TMS9900 and the Motorola 68000 had 16-bit external data busses, no multiplexing, and came in a 64-pin DIP package.

The thing that was common at this time was DIP packaging. And the number of pins on a DIP package was limited by simple geometry - a rectangular package needs a progressively longer lead from the corner pins to the semiconductor chip as the number of pins increases. This geometry constraint limited DIPs to 64-pins, practically. This limitation also helped drive the transition from rectangular DIP to the various square packaging that followed.

The Intel 8086 came in a 40-pin DIP and relied on multiplexing for its 16-bit data bus (shared with address lines). The WDC 65C816 used the same 40-pin DIP and multiplexing scheme. Neither of these 16-bit CPUs were particularly successful in these packages. The 65C816 was repackaged for the SNES as the CPU core in a QFP package. The 80286 was the successful 16-bit successor to the DIP 8086 (and 8088) in 1982, and by that time square packaging was replacing DIPs.

Your question assumes that CPUs with more than 40 pins were a rarity in the 1970s, but this was common for early 16-bit CPUs. Both the TI TMS9900 and the Motorola 68000 had 16-bit external data busses, no multiplexing, and came in a 64-pin DIP package.

The thing that was common at this time was DIP packaging. And the number of pins on a DIP package was limited by simple geometry - a rectangular package needs a progressively longer lead from the corner pins to the semiconductor chip as the number of pins increases. This geometry constraint limited DIPs to 64-pins, practically. This limitation also helped drive the transition from rectangular DIP to the various square packaging that followed.

The Intel 8086 came in a 40-pin DIP and relied on multiplexing for its 16-bit data bus (shared with address lines). The WDC 65C816 used the same 40-pin DIP and multiplexing scheme. Neither of these 16-bit CPUs were particularly successful in these packages. The 65C816 was repackaged for the SNES as the CPU core in a QFP package. The 80286 was the successful 16-bit successor to the DIP 8086 (and 8088) in 1982, and by that time square packaging was replacing DIPs.

In short, the market did not want a 16-bit CPU in a 40-pin DIP package with external demux. Fortunately, DIP soon gave way to newer packaging geometries that supported far higher pin counts.