Timeline for Repurposing the parity bit
Current License: CC BY-SA 3.0
4 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Apr 16, 2018 at 8:22 | vote | accept | rwallace | ||
| Apr 16, 2018 at 7:58 | comment | added | Jules | As an aside: I've used 9-bit wide memory for storing data on an FPGA before; it can be quite convenient at times. Particularly, with 18-bit words you can get a vector of 3x6-bit components, or 12-bit components in a 36-bit word. The particular job I was working on was a digital signage system that used RGB LEDs driven by shift registers, and 6 bits per channel was ideal for that purpose... | |
| Apr 16, 2018 at 7:31 | answer | added | Raffzahn | timeline score: 9 | |
| Apr 16, 2018 at 7:08 | history | asked | rwallace | CC BY-SA 3.0 |