Timeline for Intel 8080 and Altair 8800. 256 I/O ports, but only 7 free RST (interrupt subroutines) — how does it work?
Current License: CC BY-SA 4.0
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| Aug 26, 2023 at 18:31 | history | edited | Raffzahn | CC BY-SA 4.0 |
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| Jun 26, 2018 at 13:02 | history | edited | Raffzahn | CC BY-SA 4.0 |
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| Jun 26, 2018 at 12:39 | vote | accept | MiniMax | ||
| Jun 26, 2018 at 10:53 | comment | added | lvd |
@Raffzahn Because of data bus pullups, interrupt vector in rubber ZX Spectrum is #FF, and therefore in IM 2 mode, Z80 fetches the interrupt address from (I*256+255, I*256+256) address pair. So it's ok to supply an odd interrupt vector to Z80
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| Jun 26, 2018 at 1:02 | history | edited | Raffzahn | CC BY-SA 4.0 |
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| Jun 26, 2018 at 0:09 | comment | added | Raffzahn | @Jules I'm describeing it from a pure 8080 viewpoint. As with every other feature it can be disabled depending on the design. In fact, a logic pageing in a ROM in when /RESET is pulled is a great way to use RST0 as an additional vector (for a total of 9!). When there is a (hardware) reset, the ROM gets paged in and whatever the ROM provides at address 0 is used. But when an /INT occures and RST0 is transmitted, the RAM vector will be used - isn't it :)) | |
| Jun 25, 2018 at 23:32 | comment | added | Jules | "And it's 8, not 7, as RST0 can ofc be used for an interrupt handler" ... I wouldn't say that's so obvious, unless you understand the boot process of the Altair 8800, which is somewhat different to most more recent machines, so it's understandable to assume that RST 0 would be reserved for the reset vector. But because the Altair has RAM at address 0 and that RAM is (usually) overwritten by a bootloader on every reset, it is available for the running software to use for whatever purpose it wants. | |
| Jun 25, 2018 at 22:32 | history | edited | Raffzahn | CC BY-SA 4.0 |
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| Jun 25, 2018 at 22:24 | comment | added | Raffzahn | @lvd yes, you're right, when the 8080 sees a CALL during the first interrupt cycle it does two more fetches. Just, AFAIR it must be an even address supplied by the interrupting device - at least that's what the Z80 manual states. I have to admit, I never tried an odd one. Also, some devices are only able to deliver even more granualated vectors - like the CTC can only deliver in seps of 8, as the 3 lower bits of the vector command are used otherwise. | |
| Jun 25, 2018 at 21:21 | comment | added | lvd | As far as I know, 8259 is able to insert CALLs for i8080 as well for Z80. For both RST insertion is also OK, that might be done with the abovementioned 8214. Z80 has two more interrupt modes over i8080-compatible one, and they are numbered mode 0 (i8080 compatible), mode 1 (simply automatic RST #38 insertion by CPU itself) and mode 2 (vectored mode), numbered as per Z80 manual. The funny thing is that Z80 doesn't care which vector out of 256 ones is given him during mode 2 interrupt acknowledgement: it is only a convention for Z80 chipset to use just 128 even numbers for vectors. | |
| S Jun 25, 2018 at 21:00 | history | suggested | manassehkatz-Moving 2 Codidact | CC BY-SA 4.0 |
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| Jun 25, 2018 at 20:41 | review | Suggested edits | |||
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| Jun 25, 2018 at 18:59 | history | edited | Raffzahn | CC BY-SA 4.0 |
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| Jun 25, 2018 at 18:57 | comment | added | MiniMax |
"Not sure what 20Q or 1Q should mean here" - it is from this assembly demo code this - the out port number in the octal format (Q - octal suffix). I were thinking, that it is the keyboard port number. This link from the video description.
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| Jun 25, 2018 at 18:24 | history | answered | Raffzahn | CC BY-SA 4.0 |