Timeline for What was the first CPU with exposed pipeline?
Current License: CC BY-SA 4.0
5 events
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| Aug 7, 2018 at 14:01 | comment | added | lvd | ARM7TDMI (taken as an example) has 3-stage pipeline and PC+8 paradigm fits nicely with the pipeline: while the instruction that addresses through PC passes from fetch to execute stage, PC increments twice (as new instructions fetch through) and holds PC+8 value. In contrary, PDP-11 has neither prefetching nor pipelining and bothering with PC after the instruction fetched and has started execution shows exactly +2 increment. | |
| Aug 6, 2018 at 19:23 | comment | added | Leo B. | @supercat I see. My point is that these details expose not the pipeline but the microprogram. The famous PDP-11 backwards-self-replicating instruction 012727 would not have worked with a different microprogram. | |
| Aug 6, 2018 at 16:06 | comment | added | supercat |
@LeoB.: On the PDP-11, R7 holds the address of the next instruction. On the ARM, it holds an address 4 beyond that which unfortunately, precludes the use of PDP-11-style "immediate" addressing [since one would need an addressing mode that fetches the byte at [R15,#-4], while loading R15 with the value it already holds (writing R15 prevents the execution of the instructions at [old R15,#-4]). One could perhaps use [R15,#4]! addressing mode [post-increment, like the PDP-11] in 32-bit ARM mode, but that would require inserting an unused word between the load and the immediate value.
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| Aug 2, 2018 at 18:26 | comment | added | Leo B. | From that point of view, PDP-11 exhibited a similar level of pipeline exposure. | |
| Aug 2, 2018 at 16:53 | history | answered | lvd | CC BY-SA 4.0 |