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##The Whole Life is a Tradeoff

The Whole Life is a Tradeoff

##Consideration #1 PCB layout

Consideration #1 PCB layout

##Consideration #2 Power Supply Quality (Buffering Capacitor)

Consideration #2 Power Supply Quality (Buffering Capacitor)

##Ok, But Then Why Opposite?

Ok, But Then Why Opposite?

##The Whole Life is a Tradeoff

##Consideration #1 PCB layout

##Consideration #2 Power Supply Quality (Buffering Capacitor)

##Ok, But Then Why Opposite?

The Whole Life is a Tradeoff

Consideration #1 PCB layout

Consideration #2 Power Supply Quality (Buffering Capacitor)

Ok, But Then Why Opposite?

For simple PCB design it's quite handy if supply power and ground are on opositeopposite 'ends' of a chip (*1). Having one at the 'upper' end (where the mark is) and the other at the lower end (*2) allows a design with a power bar runing alondrunning along one side and a ground one along the other. With a little luck when routing and the usage of rails (*3) it may allow the use of single sided boards with a minimum of discrete wireingwiring (jumpers) - or at least keep a design within two layers. Multiple rows of chips lead to a design with a pair power traces (or rails) runingrunning along the middle as seen on many boards.

On the other hand, for a good power supply it's handy to have a right sized-sized capacitor as close as possible (short routing/wires) to the power supply pins to buffer switching needs. AsThe higher switching frequencies get, asthe more important this is. Placing power and ground at two adjacent pins would allow to addadding a capacitor right next to them.

Also, placing both of this pair near the middle of an edge further shortens the wire length, as the internal part of these pins (which in turn are bonded to the die) are here the shortest of all.

Of course routing of power lines will now be a rather complex among all the signals. But still managablemanageable - especially when again using railrails (*4).

##Ok, But Then Why OpositeOpposite?

It is desirable to have the same voltage between ground and power across the whole chip area (or as much as possible at least). Unlike simplified asumptionsassumptions, semiconductorsemiconductors have a rather high resistance, about 10 to 1000 times of copper. Increased by the fact that conductivityconductanc is not only defined by the material, but also conducting diameter, power distribution across a chip becomes a serious issue (*5). And no, impedance isn't of much relevance for power supply, as we do not have an alternating voltage (6).

If power would bewas supplied by adjacent pins, the region where these pins are bonded in would enjoy full voltage, while the areas at the other 'end' would get a quite lower supply resulting at least in lower maximum performance if not worse. By placeingplacing them on opositeopposite sides of the die, the voltage loss is somewhat compensated over most areas. None gets maximum voltage, but all get about the same (*7) which again is something easing circuit design of the chip.

PutingPutting both on opositeopposite positions (horzontalhorizontal (*8) or diagonal) is therefore mandatory.

It's important to note, that pins using a 'diagonal' layout (like TTL or most other) also end up in the middle of opositingopposite edges of the die - after all, it's square (mostly) and pins are bonded all arroundaround.

Bottom Line, Zilogs: Zilog's solution scales better with higher frequency and allows better signal quality, but requires a little mormore complex PCBs.

*3 - These are metal bandbands with pins in regular intercalsintervals like .6 inch or alike. With rails a, the routing of power can be eliminated for major parts of a PCB. This was even more important with early automatic routing systems removing a whole dimension of complexity.

*4 - Now standard .6" or 1" rails may not work as goodwell, but it's still better than routing them among all the signals.

*5 - ThatsThat's also the reason why these huge modern chips have not just one or a few pairs of power pins but sometimes hundretshundreds.

*7 - Yes, there is still variation due to routing and so on, but it's by default waymuch less than without this consideration.

*8 - The PIO breaks this a bit by using 11/26 instead of 11/29 in favour of keeping all Port B pins ajacentadjacent. A little variation doesn't kill the principle.

For simple PCB design it's quite handy if supply power and ground are on oposite 'ends' of a chip (*1). Having one at the 'upper' end (where the mark is) and the other at the lower end (*2) allows a design with a power bar runing alond one side and a ground one along the other. With a little luck when routing and the usage of rails (*3) it may allow the use of single sided boards with a minimum of discrete wireing (jumpers) - or at least keep a design within two layers. Multiple rows of chips lead to a design with a pair power traces (or rails) runing along the middle as seen on many boards.

On the other hand, for a good power supply it's handy to have a right sized capacitor as close as possible (short routing/wires) to the power supply pins to buffer switching needs. As higher switching frequencies get, as more important this is. Placing power and ground at two adjacent pins would allow to add a capacitor right next to them.

Also, placing both of this pair near the middle of an edge further shortens the wire length as the internal part of these pins (which in turn are bonded to the die) are here the shortest of all.

Of course routing of power lines will now be a rather complex among all the signals. But still managable - especially when again using rail (*4).

##Ok, But Then Why Oposite?

It is desirable to have the same voltage between ground and power across the whole chip area (or as much as possible at least). Unlike simplified asumptions, semiconductor have a rather high resistance, about 10 to 1000 times of copper. Increased by the fact that conductivity is not only defined by the material, but also conducting diameter, power distribution across a chip becomes a serious issue (*5). And no, impedance isn't of much relevance for power supply, as we do not have an alternating voltage (6).

If power would be supplied by adjacent pins, the region where these pins are bonded in would enjoy full voltage, while the areas at the other 'end' would get a quite lower supply resulting at least in lower maximum performance if not worse. By placeing them on oposite sides of the die the voltage loss is somewhat compensated over most areas. None gets maximum voltage, but all get about the same (*7) which again is something easing circuit design of the chip.

Puting both on oposite positions (horzontal (*8) or diagonal) is therefore mandatory.

It's important to note, that pins using a 'diagonal' layout (like TTL or most other) also end up in the middle of opositing edges of the die - after all, it's square (mostly) and pins are bonded all arround.

Bottom Line, Zilogs solution scales better with higher frequency and allows better signal quality but requires a little mor complex PCBs

*3 - These are metal band with pins in regular intercals like .6 inch or alike. With rails a the routing of power can be eliminated for major parts of a PCB. This was even more important with early automatic routing systems removing a whole dimension of complexity.

*4 - Now standard .6" or 1" rails may not work as good, but it's still better than routing them among all the signals.

*5 - Thats also the reason why these huge modern chips have not just one or a few pairs of power pins but sometimes hundrets.

*7 - Yes, there is still variation due routing and so on, but it's by default way less than without this consideration.

*8 - The PIO breaks this a bit by using 11/26 instead of 11/29 in favour of keeping all Port B pins ajacent. A little variation doesn't kill the principle.

For simple PCB design it's quite handy if supply power and ground are on opposite 'ends' of a chip (*1). Having one at the 'upper' end (where the mark is) and the other at the lower end (*2) allows a design with a power bar running along one side and a ground one along the other. With a little luck when routing and the usage of rails (*3) it may allow the use of single sided boards with a minimum of discrete wiring (jumpers) - or at least keep a design within two layers. Multiple rows of chips lead to a design with a pair power traces (or rails) running along the middle as seen on many boards.

On the other hand, for a good power supply it's handy to have a right-sized capacitor as close as possible (short routing/wires) to the power supply pins to buffer switching needs. The higher switching frequencies get, the more important this is. Placing power and ground at two adjacent pins would allow adding a capacitor right next to them.

Also, placing both of this pair near the middle of an edge further shortens the wire length, as the internal part of these pins (which in turn are bonded to the die) are here the shortest of all.

Of course routing of power lines will now be rather complex among all the signals. But still manageable - especially when again using rails (*4).

##Ok, But Then Why Opposite?

It is desirable to have the same voltage between ground and power across the whole chip area (or as much as possible at least). Unlike simplified assumptions, semiconductors have a rather high resistance, about 10 to 1000 times of copper. Increased by the fact that conductanc is not only defined by the material, but also conducting diameter, power distribution across a chip becomes a serious issue (*5). And no, impedance isn't of much relevance for power supply, as we do not have an alternating voltage (6).

If power was supplied by adjacent pins, the region where these pins are bonded in would enjoy full voltage, while the areas at the other 'end' would get a quite lower supply resulting at least in lower maximum performance if not worse. By placing them on opposite sides of the die, the voltage loss is somewhat compensated over most areas. None gets maximum voltage, but all get about the same (*7) which again is something easing circuit design of the chip.

Putting both on opposite positions (horizontal (*8) or diagonal) is therefore mandatory.

It's important to note that pins using a 'diagonal' layout (like TTL or most other) also end up in the middle of opposite edges of the die - after all, it's square (mostly) and pins are bonded all around.

Bottom Line: Zilog's solution scales better with higher frequency and allows better signal quality, but requires a little more complex PCBs.

*3 - These are metal bands with pins in regular intervals like .6 inch or alike. With rails, the routing of power can be eliminated for major parts of a PCB. This was even more important with early automatic routing systems removing a whole dimension of complexity.

*4 - Now standard .6" or 1" rails may not work as well, but it's still better than routing them among all the signals.

*5 - That's also the reason why these huge modern chips have not just one or a few pairs of power pins but sometimes hundreds.

*7 - Yes, there is still variation due to routing and so on, but it's much less than without this consideration.

*8 - The PIO breaks this a bit by using 11/26 instead of 11/29 in favour of keeping all Port B pins adjacent. A little variation doesn't kill the principle.

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It is desirable to have the same voltage between ground and power across the whole chip area (or as much as possible at least). Unlike simplified asumptions, semiconductor have a rather high resistance, about 10 to 1000 times of copper. Increased by the fact that conductivity is not only defined by the material, but also conducting diameter, power distribution across a chip becomes a serious issue (*5). And no, impedance isn't of much relevance for power supply, as we do not have an alternating voltage (6).

If power would be supplied by adjacent pins, the region where these pins are bonded in would enjoy full voltage, while the areas at the other 'end' would get a quite lower supply resulting at least in lower maximum performance if not worse. By placeing them on oposite sides of the die the voltage loss is somewhat compensated over most areas. None gets maximum voltage, but all get about the same (*6*7) which again is something easing circuit design of the chip.

Puting both on oposite positionsPuting both on oposite positions (horzontal (*8) or diagonal) is therefore mandatory.

It's important to note, that pins using a 'diagonal' layout (horizontallike TTL or diagonalmost other) as seen withalso end up in the Zilog chipsmiddle of opositing edges of the die - after all, it's square (*7mostly), but also TTLs or next to any other chip is therefore mandatory and pins are bonded all arround.

*6 - It is of course relevant if we look at digital lines.

*7 - Yes, there is still variation due routing and so on, but it's by default way less than without this consideration.

*7*8 - The PIO breaks this a bit by using 11/26 instead of 11/29 in favour of keeping all Port B pins ajacent. A little variation doesn't kill the principle.

It is desirable to have the same voltage between ground and power across the whole chip area (or as much as possible at least). Unlike simplified asumptions, semiconductor have a rather high resistance, about 10 to 1000 times of copper. Increased by the fact that conductivity is not only defined by the material, but also conducting diameter, power distribution across a chip becomes a serious issue (*5).

If power would be supplied by adjacent pins, the region where these pins are bonded in would enjoy full voltage, while the areas at the other 'end' would get a quite lower supply resulting at least in lower maximum performance if not worse. By placeing them on oposite sides of the die the voltage loss is somewhat compensated over most areas. None gets maximum voltage, but all get about the same (*6) which again is something easing circuit design of the chip.

Puting both on oposite positions (horizontal or diagonal) as seen with the Zilog chips (*7), but also TTLs or next to any other chip is therefore mandatory.

*6 - Yes, there is still variation due routing and so on, but it's by default way less than without this consideration.

*7 - The PIO breaks this a bit by using 11/26 instead of 11/29 in favour of keeping all Port B pins ajacent. A little variation doesn't kill the principle.

It is desirable to have the same voltage between ground and power across the whole chip area (or as much as possible at least). Unlike simplified asumptions, semiconductor have a rather high resistance, about 10 to 1000 times of copper. Increased by the fact that conductivity is not only defined by the material, but also conducting diameter, power distribution across a chip becomes a serious issue (*5). And no, impedance isn't of much relevance for power supply, as we do not have an alternating voltage (6).

If power would be supplied by adjacent pins, the region where these pins are bonded in would enjoy full voltage, while the areas at the other 'end' would get a quite lower supply resulting at least in lower maximum performance if not worse. By placeing them on oposite sides of the die the voltage loss is somewhat compensated over most areas. None gets maximum voltage, but all get about the same (*7) which again is something easing circuit design of the chip.

Puting both on oposite positions (horzontal (*8) or diagonal) is therefore mandatory.

It's important to note, that pins using a 'diagonal' layout (like TTL or most other) also end up in the middle of opositing edges of the die - after all, it's square (mostly) and pins are bonded all arround.

*6 - It is of course relevant if we look at digital lines.

*7 - Yes, there is still variation due routing and so on, but it's by default way less than without this consideration.

*8 - The PIO breaks this a bit by using 11/26 instead of 11/29 in favour of keeping all Port B pins ajacent. A little variation doesn't kill the principle.

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