Timeline for How did 2-chip CPUs work?
Current License: CC BY-SA 4.0
14 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Nov 20, 2020 at 0:15 | answer | added | supercat | timeline score: 3 | |
| Jun 23, 2020 at 15:58 | comment | added | davidbak | Just wanted to give a shout-out here to the ambitious but failed Intel iAPX-432 - also a two-chip CPU. Bit-aligned variable length instructions - that was easy to decode! Capability-based protection architecture (later seen in the rings/gates of the 80286). IEEE 754 floats! | |
| Aug 20, 2019 at 19:04 | answer | added | Chromatix | timeline score: 5 | |
| Apr 8, 2019 at 16:21 | vote | accept | rwallace | ||
| Apr 7, 2019 at 8:55 | answer | added | dirkt | timeline score: 5 | |
| Apr 6, 2019 at 22:46 | vote | accept | rwallace | ||
| Apr 8, 2019 at 16:21 | |||||
| Apr 6, 2019 at 18:50 | comment | added | dirkt | Then maybe make a more general question about multi-chip CPUs (or edit this one)? The F8 CPU needed three chips; the program counter register(s) (PC) and the data counter register (DC) were in the "ROM" chip. In a similar way, the F-11/J-11 control chip contains the ROM/PLA for microcode with associated control logic. | |
| Apr 6, 2019 at 16:10 | comment | added | rwallace | @another-dave All of the above. Length of wires from silicon to end pins, mechanics of connecting to the board, standard testing equipment not being designed to go above 40 pins etc. Nothing impossible, to be sure; just tricky and expensive, as I said. | |
| Apr 6, 2019 at 16:07 | comment | added | rwallace | @dirkt I picked the F11 simply as a representative example. Would be interested in other examples. As far as I can decipher the Wikipedia description, the F8 CPU is on a single chip? | |
| Apr 6, 2019 at 14:12 | comment | added | dave | To what is the "trickery and expense" with higher pin count associated? Connections to the silicon, pins on the final package, connecting the package to the motherboard? I'd have assumed the first, but on the other hand one answer below cites 80-pin chips. | |
| Apr 6, 2019 at 10:49 | answer | added | alephzero | timeline score: 8 | |
| Apr 6, 2019 at 8:57 | comment | added | dirkt | There are quite a few non-bitslice multi-chip CPUs besides the F11 (e.g. the Fairchild F8, or the F-14 CADC), and all are restrained by low pin count, and somehow have to distribute everything on multiple chips, and all end up using ways to do so. Are you interested in the F11 specifically? Because I don't think this question has a general answer for all these types of CPUs. | |
| Apr 6, 2019 at 7:35 | review | Close votes | |||
| Apr 7, 2019 at 13:29 | |||||
| Apr 6, 2019 at 0:59 | history | asked | rwallace | CC BY-SA 4.0 |