Unusual complexities
The project that prompted the question is equivalent to writing a compiler, but an unusual degree of control over the generated code is desired. You may find some of the information you need in the sources of GCC, GDB and the LLVM project, but you probably won't find all of it, which would mean you'd need to check that partial information against another source.
32-bit ARM architectures are rather complicated in this respect, having several instruction encodings. The modern cores also come in three "profiles", for processors intended for running Applications (-A suffix), embedded Microcontrollers (-M suffix) and embedded Realtime systems (-R suffix). The profile doesn't affect the instruction encoding, but it is something you have to understand to make sense of the documentation. Different cores within a profile can have different instruction timings, of course.
I looked at the reference manual for ARMv7-A and ARMv7-R, which is freely downloadable. It documents instruction availability on all the 32-bit ARM architectures. There are three encodings for many instructions (Thumb-1, Thumb-2, and ARM). However, it gets more complicated: there are "IT Blocks", prefix instructions that allow one to four Thumb-1 instructions following the prefix to be executed, or not, depending on condition codes. If you want to support ARMv7-M, which only supports Thumb instructions, that's another manual. While Thumb-2 is an extension of Thumb-1, there are cores that support Thumb-1 and Thumb-2, but leave out a few of each set of instructions, so you do need to keep track of both.
Since ThumbEE has been deprecated for over a decade and has been removed from ARMv8, I suggest you leave it out. I'd also suggest you leave out 26-bit addressing, which is long dead, and run-time selectable endianness, but those depend on how thorough you want to be.
Hit the Reference Manual(s)
I think you're going to have to compile your own tables. The reference manuals seem to have everything you need to do that. For example, I picked the ROR (register) instruction, more or less at random, to look at.
Thumb-1
ROR (register) is available in ARMv4, all the variants of ARMv5T, all the variants of ARMv6, ARMv7-A and ARMv7-R.
Thumb-2
ROR (register) is available in ARMv6T2, ARMv7-A and ARMv7-R.
ARM32
ROR (register) is available in ARMv4, all the variants of ARMv5T, all the variants of ARMv6, ARMv7-A and ARMv7-R.
Confounding factors
The different ARM cores have varying instruction timings, and most of them (other than the earliest, and the smallest modern ones) have caches. That means the effective way to tell which instruction sequences are fastest is to run them on real hardware of the correct model. That's going to make using the OP's project a lot harder.