Why do Early DRAMs (e.g. 4116) have a negative Column Address Set-up Time?

Question

Early DRAMs have a multiplexed address bus. Briefly speaking, to access a word, one needs to...

1. Put the row address on the bus, and latch it using the falling edge of /RAS signal.

2. Put the column address on the bus, and latch it using the falling edge /CAS signal.

3. The data appears at the data bus after a delay, i.e. CL, the /CAS latency.

The above process is shown in this timing diagram:

However, in the Mostek 4116 DRAM datasheet, Column Address Set-up Time, a.k.a t_ASC, the time between a valid column address and the falling edge of /CAS, is a negative number. In other words, /CAS is allowed to start falling even before the column address is stable, up to 10 nanoseconds.

This is especially problematic when interfacing devices designed for 4116 DRAM. One classic example is Texas Instruments TMS9918 video chip, of which the chip actually does start pulling /CAS low before the column address is stable. Artificial delay must be introduced to interface it with newer RAM chips.

In comparison, in the the datasheet of a modern CMOS DRAM, Oki MSM514256C, a 256K x 4-bit DRAM (circa. 1997), t_ASC is 0 nanoseconds, which basically means the /CAS is only allowed to fall as soon as the the column address is valid, which is more intuitive.

I know a negative set-up time is sometimes used in digital devices, but what is the specific design rationale of having a negative Column Address Set-up Time in 4116 DRAMs? Is it simply a side-effect (e.g. propagation delay?) of the logic details used in 4116? Is it designed to allow the timing requirement to be met more easily? A faster access speed? Or it's something else?

Answer 1

The 4116 was likely designed during in an era (or semiconductor technology node) when self-timed-delay pre-charge-evaluate NMOS logic cascades were common. (e.g. rather than synchronously or edge clocked CMOS)

The bit-line sense amps and wide column select mux had to consist of a large total gate area. Thus it would take quite awhile to precharge all of that. The column address would not be needed to pull down some selected gate path until after the precharge completed, This might take up most or all of that 20 nS using NMOS transistors that were several square microns in gate area. The column address thus need not be latched until after the end of the precharge pulse that was perhaps triggered by the falling edge of CAS.

Answer 2

(Preface: leaving out the title column makes reading tables it a bit hard)

It's all about translating labels and numbers into meaningful sentences. And there are different ways to tell a fact, and thus more nuanced details.

Timing does describe relations. Here it's about the fact, that CAS must be released at least 20 ns before RAS can be pulled again. It's the relation between these two.

Of course it could also have been described as RAS can be pulled at earliest 40 ns before CAS can be pulled, but that sounds optional.

Or translated as English sentences:

tCRP -20ns means:

"A following access indicated by RAS must allow for at least 20ns after the rising edge of CAS."

while tCRP 5nssays:

"A following access indicated by RAS may happen at least 20ns after the rising edge of CAS."

The message is the same, comes down to the story the designer wants to tell.

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P.S.: And yes, the art of speaking in timings got mostly lost since back then.

Answer 3

I will venture a guess.

Imagine /CAS and the address bus are both registered outputs clocked by the same clock. The negative setup time allows a slight clock-to-output propagation delay discrepancy between the two outputs where /CAS falling may precede the address bits becoming stable.

Moreover, there are other factors which may add propagation delay to the address bus compared to the /CAS signal. The address bus could drive many more DRAM chips than are driven by the /CAS signal. There could be multiple banks of DRAM sharing the same address bus but separate /CAS signals. Or for example a 16-bit DRAM system which allows writing to either one or both of the bytes of a 16-bit word. Such a system would likely have separate /CAS lines for each 8-bit half of the 16-bit width, but the address bus can be shared among all of the DRAM chips. Or maybe the address bus is buffered, and the negative setup time allows a bit more buffer delay for the address.

I envy this negative setup time greatly when designing with the newer DRAM chips.