At width=40, 240 pixels are generated from a nominal line width of 342; subtracting the 58/342ths of the line that is used for blanking and sync that means around 84% of each line is pixels. Using all 32 columns in one of the other modes would be slightly wider at 256 pixels for almost 90% coverage.*
The classic title-safe area per SMPTE RP 8 is the central 80% and the classic action-safe area is 90%** — i.e. it is recommended that if a TV programme puts text on screen then it shouldn't be outside of the central 80% of the screen in order to ensure that all viewers can read it, but important action can occur anywhere in the central 90%.
So it is indeed a risk to use all 40 columns and require that the user be able to read them all.
The MSX 2 adds the hardware ability to shift the entire display up to 8 pixels in any direction relative to the frame, to ameliorate.
Such as it may help for comparison, the ZX Spectrum 128k's 256 pixels are compressed into 128/228ths of the line compared to the MSX's 256/342ths, i.e. the MSX's display is about a third wider; similarly it's coming up on 20% wider than the full width of an Acorn or Amstrad CPC. The Master System has exactly*** the same pixel timing as the MSX so the risk is situations like this one where the right-hand side of the game has been cropped by the TV.
* Check out this in-depth look at TMS9918 and V9938 timing, zoom in on the diagram and observe from the TMS rows at the bottom: (i) that there are 342 clocks total per line; (ii) that the synchronisation pulse runs in the left during what the author has numbered clocks 0 to 26, followed by a left erase signal (i.e. blank and colour burst) up to clock 50 and the right erase time begins at clock 334, for 342-334+26 = 58 clocks on the part of the line without visual content.
** I can't find the primary source online; here's one of many secondary references.
*** other than that any game that scrolls horizontally probably disables the first column for a 31-column display, including Sonic as depicted.