Could a 6502 use different speeds of RAM in a single machine?

Question

I'm not sure I've entirely formed the idea in my head, but I'll ask anyway...

One of the things I learned here in RO is that the BBC gained speed by using faster RAM, thereby avoiding cycle stealing during video refresh. IIRC, this resulted in ~30% better performance.

My question is whether it would be possible to get the same performance boost using solutions that were available earlier and were cost effective at that time, that is, the ~1981 time frame.

• I assume dual-ported RAM would allow this, but was this widely available and cost competitive? Could one have a small section of dual-port and then a larger bank of "normal" RAM without issue?

• could one mix high- and low-speed parts on a single bus? Do the refresh requirements change as well, and would that preclude such solutions?

• something else I haven't thought of?

Answer 1

As to the headline question: yes.

The Acorn Electron, a convenient example because it's a BBC relative, proves this after a fashion. ROM is accessed at 2Mhz. The supplied RAM, which is shared with video, is accessed at at most 1Mhz. This is effected by slowing the CPU's clock based on its access destination.

A modification to the machine was to replace the low 8kb of address space with RAM that didn't sit behind the ULA. So it was no longer available for video but could now be written to and read by the CPU at 2Mhz.

So at that point you had a 6502 that didn't just access some areas of memory more quickly than others, but used two observably different speeds of RAM in the same machine.

Re: refresh, that counteracts leakage. So refreshes must occur within an absolute amount of real-world time. It's independent of the access speed the RAM is being used at.

Otherwise, the 6502's fixed memory access cadence obviated any need for dual-port RAM in its class of machines. It was always the case that you'd see half a cycle in which the 6502 was bus master and then half a cycle in which it wasn't. So the best solution for frictionless dual access on a 6502 machine is just to have video control the bus every other half cycle.

The BBC does this, as did the Apple II a few years before, and later machines like the Oric. Where bandwidth was insufficient with that access pattern, doing what approximately amounts to using a 16-bit bus for graphics fetching was an option: that's what the Apple IIe does in 80-column mode. Within each video access window it simultaneously fetches bytes from two physically different 8-bit portions of memory.

Answer 2

The 6502 was intended to be run a constant clock rate and the early version were 1MHz but later 2MHz and higher. Also some of the peripheral chips became faster with time but not all of the useful ones.

With 1MHz you can put any speed of RAM or ROM in there as long as it meets the setup times for read and write for the CPU. I can put a modern 10ns static RAM in a 1MHz system typically without problem but it's not going to run faster unless the system clocking is increased.

But in the late 80s they started to use some faster chips and the 2MHz 6502B and switch clocking rate dynamically between 1MHz and 2MHz depending on the address accessed, so that slower chips could also be used. You see that in the BBC Micro computer model B. The clock changing circuitry is a bit of a *** to understand because ideally the 6502 is supposed to be outputting two non-overlapping clock waveforms 01 and 02 from the input clock and I think changing the clock rate was a bit difficult without glitches. In the BBC Micro it gets stretched by half cycles to slow down rather than just going directly from 2MHz to 1MHz. It might seem the same but you have to check the circuitry which is right in the middle: http://www.goffart.co.uk/museum/schematics/bbc_b.pdf

You can see on the schematic that it has address decoding from IC24 (LS138) through to the inverter of IC33 (LS04) and that's what triggers the clock to slow down from 2MHz to 1MHz, but it's quite complicated because the circuit with all the flip flops depends on the 01 output of the 6502 as well as the clock counter chain input.

I don't think any machine from the era can detect magically how fast the memory is and speed up or slow down, and especially using the 6502 which doesn't have a very good wait system to insert cycles anyway. It has RDY, but it's rather cumbersome.

The BBC has fairly fast dynamic RAM which is refreshed by video access. Typically the video chip is accessing every RAM row so nothing else is needed for refresh. The CPU would access the RAM transparently on every half cycle so there's no such thing as stealing access from the video system. They're accessing memory in alternation. That's what many home computers did at that time.

Also DRAMs at that time were not that critical with refresh. You can stop refreshing them for a few seconds with hardly any data corruption. That's from personal experience with 4164 and other DRAMs. The charge leaks away over a few seconds.

In the BBC schematic IC45 is selecting the row and column addresses for the RAM in a cycle so it alternates between video and CPU access: the LS139 chip's B input is connected to the 2MHz clock so the RAM address source selecting is done based on the clock state so the CPU is getting the RAM for half the time.

Back in the 80s dual-port RAMs were like 256 bytes, and really freaking expensive.