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In short, are banks 20h/40h/60h accessible in mode 1?

The Pan Docs state that when in mode 1, those banks become accessible.

"...on large carts (using the secondary banking register to specify the upper ROM Bank bits), the same happens for banks 20h, 40h, and 60h, as this register would need to be 00h for those addresses. Any attempt to address these ROM Banks will select Bank 21h, 41h, and 61h instead. The only way to access banks 20h, 40h or 60h is to enter mode 1, which remaps the 0000-3FFF range."

They clearly say that mode 1 remaps the 0000-3FFF range, which I haven't seen other sources say. This is also confusing because mode 1 affects the RAM banks. The Pan Docs say that mode 1 behaves differently for a small ROM/large RAM, and large ROM/small RAM.

"In mode 1, the behavior differs depending on whether the current cart is a "large RAM" cart (>8kB RAM) or "large ROM" cart (1 MB or larger). For large RAM carts, switching to mode 1 enables RAM banking and (if RAM is enabled) immediately switches the A000-BFFF RAM area to the bank selected by the 2-bit secondary banking register."

"For "large ROM" carts, mode 1 has the 4000-7FFF banked ROM area behave the same as mode 0, but additionally the "unbankable" "bank 0" area 0000-3FFF is now also affected by the 2-bit secondary banking register, meaning it can now be switched between banks 00h, 20h, 40h, and 60h. These banks are inaccessible in mode 0 - they cannot be mapped to the 4000-7FFF banked ROM area."

However, they don't address the large ROM/large RAM case; is it possible? If so, how does the secondary bank register behave in mode 1?

Other sources that I found simply say that banks 20h/40h/60h are inaccessible, and don't mention the 0000-3FFF remapping. They say that in mode 0, RAM banking is disabled and the full ROM banking is enabled, and in mode 1 RAM banking is enabled and you get limited ROM banking. Basically, mode 0 is max 2MB ROM/8KB RAM, and mode 1 is max 512KB ROM/32KB RAM.

So which is true?

Links:

Pan Docs

A retrocomputing answer

The GameBoy CPU Manual

**Edit: ** As a follow-up question, if the Pan Docs are correct, how does the mapping work exactly in mode 1 large ROM? Does the second register control only the mapping of the 0000-3FFF range, and your second range is limited to 31 banks, or does it work the same as in mode 0 but also remaps the 0000-3FFF range?

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If I understand the Pan Docs correctly, they are trying to tell you that when you have one of banks 1 to 1Fh mapped into 4000-7FFF, you get bank 0 at 0000-3FFF. If you have one of banks 21 to 3F mapped into 4000-7FFF, you get bank 20 at 0000-3FFF. You get bank 40 at 0000-3FFF if you have one of banks 41 to 5F mapped into 0000-3FFF and finally you get bank 60 mapped into 0000-3FFF if you choose one of banks 61 to 7F into 4000-7FFF.

You can also view it from a different angle: Mode 1 is intended for 32KB RAM cards. The use for "big ROM cartridges" is a kind of abuse of the MBC1. So if a creative cartridge manufacturer connects the output bits of the MBC1 which are intended to be wired to the top bits address of the static RAM chip (and carry the contents of the secondary mapping register all the time) to the top address bits of the ROM instead, you effectively get 4 sets of 32 banks each, with the first bank visible at 0000-3FFF and the other 31 banks can be selected for 4000-7FFF.

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