I have discovered that the DEC PDP-10 used a floating-point format that differed from IEEE-754 in an interesting way.

IEEE-754 is like sign-magnitude representation. The only difference between a positive value and its negative is the value of the MSB of the word. Assuming no NaNs, if you use an integer subtractor to compare two IEEE floats, the compare operation yields the correct result in 3 out of 4 cases. The case where the integer compare result is wrong is when both values are negative.

The DEC PDP-10 had the same mantissa with "hidden 1 bit", offset binary exponent to the left of the mantissa, but when the numbers were negative, the PDP-10 represented that value as the 2's complement of the positive value. So there was no "-0" representation (just one 0) and the integer compare operation worked in any case.

This is clever. I wonder what other early computers may have used this and why didn't this catch on with IEEE?

If you combine this clever formatting with floats with denormals, you can have a floating-point representation that is monotonic mapping that is a piecewise-linear approximation to the arcsinh() function when mapping the floating-point value to an integer having the same bit pattern in the word. Seems like a clever idea missed by whatever IEEE committee that first came up with 754.

I suppose they wanted "-0" so that if an operation like 1/x was done, they would know whether to use +INF or -INF, but if you leave that "feature" out and leave out NaNs, this format can assign every bit pattern to a numerical value that is a strictly-increasing mapping and that seems like a valuable feature. Every bit pattern is a number and a unique number. No NaNs or INFs or other goofy bit patterns to cause an exception.

  • found this interesting. Commented Apr 13, 2017 at 8:02
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    This is rather "futurecomputing", but it relates to your idea of piecewise approximation of a function. The discussion of the new number format starts at about 16 minutes in. Here is the sigmoid function trick.
    – Leo B.
    Commented Apr 13, 2017 at 15:44
  • Actually -0 is useful when you need to differentiate the reason why the result was positive or negative, for example when working with denormals or when calculating limits from left or right of zero, which is also important in derivatives and integrals. Besides x/+∞ and x/-∞ will produce different results. Same to x/-0 and x/+0
    – phuclv
    Commented Mar 28, 2022 at 15:59

5 Answers 5


Over the years, I have seen some really innovative ideas originally produced by the engineers at DEC (Digital Equipment Corporation).

They were the IBM or later the Apple of their day. With custom hardware and a completely different implementation strategies.

Take the widely implemented VTxxx terminal types. Though almost no one uses the VT420 anymore, it was one of the first color capable TTYs. It didn't use ANSI based color though.

Digital also made harddrives which had removable platter packs. Drive electronics and motors were separately replaceable from data storage. Sadly they were very heavy -- washing machine sized, only talked to DEC equipment, and were really expensive. SyQuest and Iomega both tried to implement solutions of this nature in the mid 90's. Both of which lost to CD's.

So back to your question.

Standards are heavily driven by industry players. Standards exist to validate the status quo. They are not usually driven by the best solution, but by the solution which is the most agreeable to all the people at the table. This is also why standards take so long to ratify and in many cases the market has decided prior to the ratification.

By the time IEEE-754 was finalized in 1985, DEC was no longer the huge powerhouse they once were. The market was flooded with 'cheap' desktop computers. Massive Mainframes and Big Iron were on the way out.

This quote from the IEE-754-1985 standard's wiki page gives the correct sense of the issue when looked at with the above context..."It was implemented in software, in the form of floating-point libraries, and in hardware, in the instructions of many CPUs and FPUs. The first integrated circuit to implement the draft of what was to become IEEE 754-1985 was the Intel 8087." Emphasis added by me. But it shows who WAS at the table.

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    There was a 'joke' in the computer industry from the late 80's to early 90's which said "The greatest thing about computer standards is that there are so many to choose from!" Commented Apr 15, 2017 at 14:01
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    Interestingly enough, Honeywell used the replaceable platter system on their Fox line of computers as well. Their system was only 2 or 3 platters, while the DEC had 10 platters, iirc. The platters were smaller as well. Never measured them, but the Honeywell was about 12" and the DEC was closer to 15". The disk pack was a lot lighter to carry around too :)
    – user4511
    Commented Apr 16, 2017 at 6:06
  • Yeah the DEC pack was made out of 6-7 aluminum platters that were about 3/8 of an inch thick which had the magnetic surface bonded to them. The super light, very refined aluminum we have today didn't exist or was very expensive. Unfortunately that gave it a huge rotational momentum, a thick platter was used so that the platter did not separate at speed. Tracks on the platter with very wide to because the read heads were so large. Commented Apr 16, 2017 at 15:21
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    Much as I am a hardcore fan of DEC engineering, the removable-pack disk drives were OEM'd by DEC. From info on the web: RP01, RP02: Memorex; RP03, RP04: Sperry Univac; RP05, RP06: Memorex. The single-platter RK05 (I had one entirely to myself - 1 million PDP-11 words, wow! - when I started work at DEC) was DEC-designed but based on an IBM 2315.
    – dave
    Commented Aug 31, 2019 at 17:12
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    Also, the VT420 was a monochrome terminal. I think you're thinking of the VT340: 16 colours (from a palette of 4096), usable as such from graphics mode (regis, sixels) only.
    – dave
    Commented Aug 31, 2019 at 19:22

This page has a list of various floating point formats for a number of different machines. Having skimmed it, I must say that the DEC 10 format seems quite rare. None of the architectures I have significant experience of used anything similar.

The DEC 10 scheme has the advantage that you can use ordinary integer compares, but it has the disadvantage that normalisation is more complex. With the sign and magnitude version, all you have to do is look for the leading 1 and the normalised mantissa is the bits to the right of that 1. With the DEC 10 scheme, this still works for positive numbers but for negative numbers, you need to look for the first 0 instead. Whereas comparisons are quite common, normalisation has to happen on every single floating point arithmetic operation, sometimes more than once.

Furthermore, in modern microprocessors, at least, floating point operations tend to be done in separate coprocessor modules that started out literally as separate chips. In such cases, the advantage of being able to reuse integer compares is moot.

  • yes, i have discovered that page, too, as i indicated in my comment. i would say, that the way to deal with the "2's complement" floating-point is to simply negate the value if it is positive (remembering that) and treat it like the "sign-magnitude" floating-point (which is what the IEEE-754 is). Commented Apr 13, 2017 at 19:21

If you will allow your attention to be extended to formats implemented in software: The Borland Database Engine uses a similar scheme to encode floating-point numbers in its tables, in order to more easily create and sort keys, especially compound keys.

In Borland Paradox (*.DB) tables, the BDE encodes its Number (N) type as a 64-bit floating-point value, with a sign bit, an 11-bit exponent, and a 53-bit fraction. (I know, that adds up to 65 bits. Keep reading.) The exponent is coded as an excess-1024 integer, so that an exponent of 0 is coded as 0x400. The fraction is normalized to have no leading zeros, adjusting the exponent as necessary. The high-order bit of the fraction is not stored since it is always one. This reduces the fraction storage requirement to 52 bits.

For a positive value, the sign bit is set to one. For a negative value, the positive value is formed and the entire 64 bits complemented (not negated as one might expect).

Zero is encoded as 0x 8000 0000 0000 0000.

This encoding maps the entire range of floating-point values monotonically onto the unsigned 64-bit integers, allowing very speedy comparison and sorting of Number type values without the need to interpret or decode them.

The BDE generally encodes each of its data types so that its sort order maps monotonically onto unsigned integers. This allows it to form compound keys by simply concatenating the field values into one binary string.

  • i think that format is called "offset binary". Commented May 31, 2017 at 15:48
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    The described format is similar to offset binary but is distinguished by having two encodings for zero (0x 8000 0000 0000 0000 and the unused 0x 7FFF FFFF FFFF FFFF). That is, the negative number offset differs by 1 from the positive number offset. Commented May 31, 2017 at 18:33
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    oh, sorta like one's complement. Commented May 31, 2017 at 22:05
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    Well, not sorta like. It is a one's complement. - I have no authority on this but I believe the authors used 'complement' instead of 'negative' because manipulating 64 bits on the 80x86 involves multiple-precision in software and they did not want to fiddle with carry bits. Commented May 31, 2017 at 23:49
  • well, sorta like because it's float and not fixed, i presume. and also it's sorta like because it is also offset binary. so if it was fixed point, we would call that "one's complement offset binary". one reason to use one's complement for negation instead of two's complement, is so that negation need not test for that nasty case of 0x8000... (or in your case 0x0000...). you can continue to use your negation in your regular chip and you're only off by one LSB. and you didn't have to test if you negated 0x8000 (which is an overflow). Commented Jun 1, 2017 at 2:35

I am documenting a file format that uses 32-bit floating point data in a DEC, Intel and SGI/MIPS environments and just created an image that might help document the different storage formats for floating point numbers.

enter image description here

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    Welcome on the site! Please make your table more clear, there nothing about what the numbers mean there.
    – peterh
    Commented Aug 31, 2019 at 16:59
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    This doesn't answer the question; both "Intel" and "SGI/MIPS" clearly use a different format to DEC (which I assume is the PDP-10 format).
    – wizzwizz4
    Commented Aug 31, 2019 at 17:48
  • Intel and SGI/MIPS seem to be the same representation, just with differing storage order. Commented Sep 3, 2019 at 16:27

separate sign bit allows very easy abs value extraction which can have huge impact on performance as many floating point operations need to handle sign separately.

That means less gates and or better processing speed.

Simple example is mantissa bit shifting (which is used for almost all FPU operations). Absolute value can be bit-shifted directly (injecting zeros) but two's complement needs to copy the highest bit for bit shift right instead.

Other operations (like multiplication) need to handle negative two's complement values in a different way than positive which leads to more circuitry and or case code.

Also using lower bit-width ALU for IEEE float/double SW emulation need to stack up more operations (like for big integers) which is much more easier with separate sign (for similar reasons)

So I assume that was the major reason to chose current FPU representation by IEEE ...

  • well, i fully disagree that signed-magnitude is a better representation for the mantissa than 2's complement. add and sub happens far more often than abs. and again, the compare operation with the current IEEE works in 3 out of 4 cases, but gives the wrong answer when both quantities are negative. Commented Aug 31, 2019 at 20:25
  • @robertbristow-johnson add and sub is more common that is true but for floats you need bit shift to common exponent first ...
    – Spektre
    Commented Aug 31, 2019 at 22:49
  • yes, but you can arithmetically shift the two's complement version just as well as the sign-magnitude version. Commented Sep 1, 2019 at 0:39
  • @robertbristow-johnson yes but ... for HW implementation either use more gates or you need dynamic propagating gate and different circuitry for shift directions ... for SW you need much more operations on per ALU word basis if SAR is not implemented ( x>>1 vs. ((x>>1)&0x7F...F)|(x&0x80...0) )
    – Spektre
    Commented Sep 1, 2019 at 7:48
  • well, ((x>>1)&0x7F...F)|(x&0x80...0) seems to be a wire in feedback to the MSB, vs. a zero shifted in from the left. of course the exponent has to be taken out and the gap between the sign bit s and mantissa has to be closed around the *"hidden 1" (which is really the inverted sign bit ~s). but that two's complement number is more ready for mathematical rock 'n roll than signed-magnitude. Commented Sep 1, 2019 at 8:55

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