I have discovered that the DEC PDP-10 used a floating-point format that differed from IEEE-754 in an interesting way.
IEEE-754 is like sign-magnitude representation. The only difference between a positive value and its negative is the value of the MSB of the word. Assuming no
NaNs, if you use an integer subtractor to compare two IEEE floats, the compare operation yields the correct result in 3 out of 4 cases. The case where the integer compare result is wrong is when both values are negative.
The DEC PDP-10 had the same mantissa with "hidden 1 bit", offset binary exponent to the left of the mantissa, but when the numbers were negative, the PDP-10 represented that value as the 2's complement of the positive value. So there was no "-0" representation (just one 0) and the integer compare operation worked in any case.
This is clever. I wonder what other early computers may have used this and why didn't this catch on with IEEE?
If you combine this clever formatting with floats with denormals, you can have a floating-point representation that is monotonic mapping that is a piecewise-linear approximation to the
arcsinh() function when mapping the floating-point value to an integer having the same bit pattern in the word. Seems like a clever idea missed by whatever IEEE committee that first came up with 754.
I suppose they wanted "-0" so that if an operation like
1/x was done, they would know whether to use
-INF, but if you leave that "feature" out and leave out
NaNs, this format can assign every bit pattern to a numerical value that is a strictly-increasing mapping and that seems like a valuable feature. Every bit pattern is a number and a unique number. No
INFs or other goofy bit patterns to cause an exception.