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In Z80 memory read cycle is three T cycles, but, 2nd cycle only does "WAIT", and it appears timing would work with just two cycles unless the "WAIT" does something important. What is the reason memory read cycle is three T cycles?

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The second cycle holds the requested address and control signals; it also samples WAIT in case a pause is being requested.

So it acts to give the component being addressed enough time to respond — you can [almost*] pick a processor clock speed based on the arithmetic that however many microseconds your RAM/etc needs to respond to a read or write should dictate the length of three clock cycles. Having that dictate two rather than three doesn’t make a huge difference.

* at least if the opcode read part of an M1 weren’t two cycles long. Some machines — including those confirming to the MSX standard — stretch the M1 read to three via WAIT in order to regularise it.

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    Thanks for answer. I corroborated what you said, that the RAM/component being addressed would be so slow that an extra cycle is required, "Way back when, memory/IO etc was slow, e.g. it could take 500ns (or more) from valid address/chip select to having valid read data from the memory chip - so adding a WAIT state (or 2 or ...) would give one extra clock (or more) for the data to be valid. " eevblog.com/forum/projects/…. This seems counter-intuitive to me because it seems like it would be faster, but I guess it is the case.
    – BipedalJoe
    Commented Dec 9, 2022 at 15:29
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    Great answer overall! Would not have thought of that myself.
    – BipedalJoe
    Commented Dec 9, 2022 at 15:30
  • They generally don't stretch it to make it regular, they stretch it because at 3.5MHz or so the instruction fetch was a tiny bit too fast for the cheap RAM of the time. Stretching just that cycle reduced the memory wait hit a fair bit
    – Alan Cox
    Commented Dec 23, 2022 at 18:13
  • @AlanCox I think we’re saying the same thing: that not having one sort of access be a third shorter than the rest is the objective. But maybe it’s poorly phrased, in terms of suggesting that making things regular is a goal in itself, rather than a consequence of another objective.
    – Tommy
    Commented Dec 24, 2022 at 19:51

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