[As I understand the question it asks for a chip just holding Mask programmed ROM and (some) RAM, not something like the well known 6530 (*1) which also provides additional peripherals. Right?]
Not really.
Well, to my knowledge the only one that may fit somewhat better than the 6530 would be Valvo/Signetics' 2656 System Memory Interface. It holds 2 KiB of ROM and 128 Bytes of RAM - but also a programmable chip select and a clock generator. So no generic I/O or devices like timers or interrupt controllers, but still replacing (at least) two other support chips.
A pure RAM/ROM chip is simply missing the point.
Why is that?
Any device (computer) that only needs a few bytes (<256) of RAM is almost exclusive what today would be called embedded. And using ROM even more a device intended to sell in large numbers (otherwise EPROM would it do). If there's one thing any kind of embedded needs then it is I/O. There is never enough I/O. So just offering RAM/ROM isn't as appealing on it's own. Add some I/O and designer will start to dream.
Developers aren't perfect
Also, it's unlikely that software works right away. ROM only chips can with be replaced by EPROM during development with little to no changed (patches) in board design. Any combi-chip (ROM + more) would mean that prototypes need different boards and/or additional emulation boards to use EPROM instead of ROM and handle the other components alike. A perfect way to introduce even more trouble during development.
The fact that there are only about 50 variants of 6530 ROM are known does tell a story.
Then why 6530
Considering that the 6530 is the outlier - especially as there are not many like it. Sure, the high integration was a selling point for the 6502, enabling two chip-systems (*2) - still, Motorola's 6801 offered even more ports in addition to ROM and RAM (*3) in a single chip, so how come?
It may help to look into history. In this case how MOS (or more correct it's CPU 'division') came to be and developed. Most of the involved engineers were originally part of the 6800 (and 6820) development team at Motorola, so quite informed about that CPU and other components. Heck, they even went with the same numbering scheme as Motorola their devices - like 2x for parallel, 3x for ROM or 5x for serial. Also note how neatly the 6530 fit the numbering for a ROM instead a complex device (4x).
Motorola had a whole family of components in production or planned - in total more than 30 different chips as part of their "total product family strategy" (*4). MOS as a small startup didn't have the capacity to come even close. They barely had the capacity for a CPU with two bus interfaces (6501/02) and a parallel port (6520, a functional clone of the 6820 (*5)). Creating single chip controllers was already discussed with customers at Motorola - and Mr. Peddle being part of that group(*6).
In 1975 packaging a CPU and RAM and ROM and IO into a single chip was outside the capabilities of Motorola and even more of MOS. But packaging all in two would be possible - and that's what MOS did. Two chips holding a CPU, 1 KiB of ROM, 64 byte of RAM, timer and parallel I/O.
A remarkable point here might be that Motorola did the same not much later. Except, they integrated 128 Bytes of RAM into the CPU, now called 6802 (*7) and added the 6846 with 2 KiB of ROM, 3 timer and parallel I/O (*8).
I would like to believe that the engineers at MOS also wanted wanted to go the very same way - after all the 6502 was, like the 6800, focused on embedded application. Though, history decided that that path never happened(*9), but that's a different story.
So bottom line: It was a way to get as close as possible to a single chip controller at a time when technology wasn't ready.
And Intel?
Intel saw whats going on and reacted in 1977 together with their new 8085 CPU with not one but three similar chips, all based on the existing 8255 parallel port:
- 8155/56 - 256 Byte RAM + Timer + 22 I/O
- 8355 - 2 KiB ROM + 16 I/O
- 8755 - 2 KiB EPROM + 16 I/O
Especially the later two were very welcome for embedded developers, as now no longer extreme expensive special versions (like 68701) or emulator boards were needed during development to use EPROM in a design that later should use ROM. 8355 and 8755 behaved exactly the same - except the 8755 could be (re)programmed over and over. Quite handy. Also, all those chips demultiplexed the 8085 bus internally, so no glue logic needed. There was even the 8185 demultiplexing 1 KiB RAM chip. It were those parts that made the 8085 quite competitive against the Z80 in embedded designs as they saved much glue logic by just selecting the right variant.
Intel did, other than Motorola, not design single chip systems based on the 8080/85/86 (*10), but focused instead on 8048/51 lines.
Late Arrival
Intel also provides what I would think of as the latest combination of ROM and I/O with their 1981 introduced "OS-Processors", the
- 80130 iRMX Operating System Processor and the
- 80150 CP/M-86 Operating System Processor.
Both packed a 16 KiB ROM, a 8259 PIC, a 8254 Timer and Multibus bus controller into a 40 pin package. The ROM held the iRMX kernel (80130) or CP/M (including BIOS) (*11).
After 1982 the time window for "ROM-Plus-Chips" had closed - at least I don't know any later. Single chip controllers held the low end, while anything past a toaster would incorporate either large ROMs or most likely be loaded from some media anyway.
What's the deal with the 2656
While also holding ROM and RAM, it forgoes the I/O part, but add clock generator (*12) and a mask programmable chip select unit. That way, peripheral devices but also more RAM or ROM could be added without needing glue logic. Quite an advantage for system designers.
Where the 6502/6530 or 6802/6846 combos are all about reducing a minimal system, like a two chip micro controller, the Valvo/Signetics variant is intended to support a larger system, one with many additional peripherals, like a two chip SoC.
What gives?
Either way, they are about a very small window at a time where technology wasn't advanced enough to integrate all of that into a single device and at the same time applications were still tidy enough to get along with such small resources.
*1 - The 6532 with more RAM instead of ROM is a later device.
*2 - Think Commodore's Chessmate, based on 6504+6530 - but also additional 256 byes of RAM and 4 KiB or ROM
*3 - And solves the development problem with it's 68701 variant
*4 - Motorola, developed a "total product family" strategy for their 6800, based around the idea to create dedicated peripheral chips and selling problem specific sets thereof as a customer tailored package. Of course that only works with large customers. Intel's strategy was quite similar, although later and they saw themself less involved in a customers design.
*5 - Not really a surprise as Mr. Mensch was at Motorola responsible for the 6820 design :)
*6 - Mr. Peddle being strong sales orientated was also who convinced Atari to go with the 6504/6532 combo for their upcoming console project.
*7 - The numbering may also give a hint that it was seen as intermediate step producing a two chip solution until the 6801 could be ready, incorporating all of that into a single chip.
*8 - Notably not numbered as ROM (3x), as MOS did, but complex (4x).
*9 - Now MOS' licensee Rockwell did continue that development with several single chip version - as well as the infamous bit operations.
*10 - The 80186/188 is, other than often claimed, not a micro controller but a system on a chip (SoC), as it incorporates most core components of a computer system (DMA, chip select and wait state generation) but no I/O or ROM/RAM, either being essential for a controller.
(Though later sub versions did add a few interfaces, but that's been at a time when the 186 was only found in high end embedded)
*11 - Slapping an 80188 (0r 186), an 80150, a 2 KiB boot EPROM and 1 MiB of RAM would make a great base for a real compact, good owered CP/M-86 system. One item on my dream-todo-list :)
*12 - Unlike the 6502, the 2650 did not have a build in clock generator, so adding it saved at least one dedicated chip.
