What exactly was the Amiga Ranger?

Question

Amiga's history includes something called "Ranger" that supposedly was either meant to be the next generation system to be released after the Amiga 1000 was released, or the codename for the next version of the custom chipset.

The name was in use till 1987, when the Los Gatos labs were closed and development of the Amiga was moved to Pennsylvania (and Jay Miner left). Today, the slow-fast memory area is still occasionally referred to as the "Ranger" RAM.

Ranger is certainly not AGA, since that should be a later project started around 1990.

So... what is known of this system/chipset? Was it ever officially mentioned in (for example) developer's documentation or DevCon papers? Was there ever a description of the intended features?

Answer 1

Ranger was to be the next generation Amiga, which the original West Coast Amiga engineers began working on in 1986-87, following the release of the Amiga 1000. Jay Miner improved the graphics chipset for Ranger to address the twin problems of chip (i.e. Graphics, Sound, DMA) RAM memory space and bandwidth in the Amiga 1000.

The Original Amiga chipset (OCS) allowed a maximum of 512K of chip RAM. This was recognized early on as too limiting, and the Ranger was enhanced to support 2M chip RAM. Additionally, Ranger was designed to make use of VRAM in order to improve the memory bandwidth available for graphics. This would allow for more bitplanes (up to 7) and higher display resolutions (up to 1024x1024). According to the Wikipedia article on Ranger, work on the chipset enhancements was completed before Jay Miner departed Commodore. Other enhancements such as a full 32-bit 68020 CPU were also contemplated for Ranger, but it is not clear how far that work ever got, and Commodore management chose a different path forward.

Because of the cost premium of VRAM vs. DRAM at the time, Commodore management decided to drop Ranger in favor of the Commodore-West Germany project to deliver a more expandable and professional Amiga system in the form of the A2000, while continuing to use the OCS. Noting that there was still no solution to the 512K chip RAM limit, Commodore quickly followed the A2000 release with an enhanced Agnus chip supporting 1M of chip RAM. Later, through the introduction of the Enhanced Amiga Chipset (ECS), the Ranger capability of supporting 2M chip RAM would be realized. This was first shipped along with the Amiga A3000.

Eventually, the Pandora project gained traction within Commodore. This project sought to offer more graphics bandwidth for enhanced resolutions, colors, bit-planes, sprites, and playfields, much like Ranger had sought to do several years earlier. Pandora would eventually be delivered as the Advanced Amiga Graphics Architecture (AGA) chipset found in the Amiga A4000, A1200, and CD32. AGA accomplished much of what was intended for Ranger, if not more in certain respects. However, it was delivered 5 years later and at a time when other bigger industry players had largely caught up to the Amiga's original graphical abilities. The failure to deliver the more advanced graphics chipset sooner is often cited as contributing to the decline of the Amiga and Commodore in the 1990s.

Dave Haynie created a specification for the never delivered Amiga A3000+ in 1991. This could have been the first machine to use Pandora, and so the specification contains some detailed early descriptions of it.

Answer 2

Ranger was going to be the next generation of the Amiga chipset after Original Chipset (OCS). It was based on the 68010 CPU and supports 2MB chipram. The new chipset would have 128 bit color registers, to support 7-bit color depths and would be capable to show 7-bit colors in 1024x1024 resolution. the high memory bandwidth required for this enhancement would be provided using VRAM chips. Commodore preferred to cancel the project due to the high price of the chipset. This was mostly because of expensive VRAM. Instead they release Enhanced Chipset in 1990 (ECS) which was a slightly improved OCS, so that most people know ECS as a 2MB OCS.

They started another project AAA in 1988 for 3rd generation chipset which retains the VRAM idea. When they realized they did't have the resources to complete AAA in time, they quickly developed and released a reduced version named AA (or AGA) in 1992 to catch up with the competition and they failed.

Presumably, Ranger - if it hadn't been cancelled - would be something similar to AGA but would have been available earlier.

Answer 3

Answering my own question as a way to spur up discussion two years later...

Based on this question and its accepted answer here: What are the Ultra-Highres registers in ECS and AGA for? , namely, the fact that AGA, and perhaps ECS already, has a DUAL/UHRES mode that is meant to drive an external CLUT/DAC connected to Vram to generate a second, high-resolution, display independently of the one generated by Denise/Lisa, I'm now convinced that indeed the Ranger chipset may actually have been implemented as either ECS or AGA.

In fact, these are reportedly the feature that Ranger had (1):

• The chip RAM maximum being 2MB rather than 512K.
• The possibility for a 1024x1024 non-interlaced display.
• The use of VRam to attain the above resolution.

ECS has:

• 2MB for chip RAM maximum.
• The 35ns SuperHires mode, which prove that it's fast enough to go above the ~ 700 pixel horizontal resolution that OCS can do (with overscan).
• a "DUAL" bit in register BEAMCOM0 (introduced in ECS) to enable a mode that is described as a "Special ultra resolution mode" (briefly mentioned in the RKM: Hardware book, 3rd edition, but never described in detail).

(Note that Alice in AGA isn't much more than ECS's Super Agnus with the ability to run a 2-cycles Fast Page mode access on a 32bit wide bus for bitplane and sprite data only and very little more than that).

IMHO it may very well be that after Jay Miner left Commodore in 1987/88 when Los Gatos closed, Commodore did indeed use his design for "Ranger" and implemented a version of the design already in ECS with Super Agnus, and then later in Alice (with the version in ECS perhaps being buggy or incomplete, and the version in AGA being instead stable enough to being documented in the official list of the chipset registers).

... except then they never went on releasing a system that actually used the VRam mode (due to requiring RTG in software? due to the usual lack of vision?), least implement a new custom chip to drive the VRam (*).

Thoughts?

Addendum: the internal memo describing the AAA chipset says:

AAA is designed to be largely register compatible with the ECS chip set. Most of the RGA registers from ECS are supported. The ECS “Ultra hires” registers have been eliminated, as they were never supported in actual practice. Some other display-generation details of ECS are no longer required or supported in AAA.

So it looks like this feature has ben around since ECS.

(*):

• could this VRam driver/CLUT/DAC "external circuitry" implementation actually be the Kelly chip originally developed for AGA?

• could it be that the 0xC000000 "slow-fast RAM" memory is known as the "Ranger RAM" because this is where the VRam was supposed to be mapped in the memory map. VRam still needs to be accessible as normal RAM too, after all.

Answer 4

The Amiga 1000 era VRAM chips had 4-bit data pins and 4-bit serial pins. I think this is shown in the A2024 patent. On the patent, they keep them D0-D3 but I think it's easy to imagine eight chips arranged as 4x2 where the 4 wide make a 16-bit bus and the two tall make two serial busses that are muxed with BLANK and the pixel clock (28MHz on Ranger?).

https://patents.google.com/patent/US4851826A/en

Whether you mux these into 1 bpp or 2 bpp doesn't matter -- the latter only adds one chip.

So, ECS/AGA Agnus could emit either 78 or 7A on the RGA bus to trigger VRAM for the "bitplane" and "sprite". This is on %0001111x, so 'x' is 'BITPLANE' or 'SPRITE'. It would also have to emit the address for the VRAM on the DRAM busses just like a normal DMA action (and I believe these happen fairly early like around cycle 2 or 3?). The VRAM latches the 1024 bits into a buffer and then streams them out when it get's a pixel clock. This would probably just be an AND of the 14MHz clock and the H/VSYNC? Seems simple enough for someone to knock together a prototype...