Questions tagged [cpu-flag-bits]

Condition flags describing the state of the CPU or the result of an operation it performed.

Filter by
Sorted by
Tagged with
6 votes
1 answer

Which CPU was the first to clear the carry and overflow bits after performing logical operations?

As I work on implementing support for old architectures for the Reko decompiler ( I notice over and over how consistently most 1980's CPUs echo a pattern. Since an ...
23 votes
1 answer

How is FSTSW AX implemented on the 80286/80287?

The x87 instruction set does not support direct transfers between general purpose registers and floating point registers. This is mainly a consequence of the 8087/80287/80387 being a separate chip ...
7 votes
1 answer

What CPU architecture was first to implement 'inverted borrow' carry flag during subtractions?

Background In two's complement arithmetics, if one wants to calculate a subtraction having only an adder that calculates {cout,result}=full_adder(arg1,arg2,cin), where cin and cout are incoming and ...
4 votes
1 answer

Why 8086/8088 has OF in a high Flags byte?

In 8086, OF is put not into low Flags byte as other flags but separated in the second (high) byte. This is followed then in all the x86 line. Beside the possible historical reasons, this looks highly ...
11 votes
3 answers

Behavior of the zero and negative/sign flags on classic instruction sets

It seems to me that there's effectively two ways that the zero bit could work. Z is set iff the result of a computation is mathematically equal to 0. Z is set iff a bit pattern consisting entirely of ...
2 votes
1 answer

Does the 6502's TXS and TSX affect flags or not?

Title says it all really. Some documentation claims that the S and Z flags are affected by both TXS and TSX, just as with all other transfer commands. Other documentation suggests that neither TXS nor ...
20 votes
5 answers

Why does the Z80 have a half-carry bit?

The Z80 apparently had a 4-bit ALU, and computes 8-bit values in two stages. The half-carry bit preserves the carry from bits 3 to 4. Why did the designers of this chip choose to preserve that value ...