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52

LOADALL is an undocumented instruction available on the 80286, 80386 and some 486 clones. It provides a means to load all the CPU's registers in one operation, including normally-inaccessible registers (descriptor caches). Its significance is that it allows extended memory to be accessed on a 286 without switching to protected mode. On a 8086, memory is ...


41

What it boils down to is that, unlike in a flat addressing model, there are multiple types of pointers: near - 16-bit (16-bit offset only.) far - 32-bit (16-bit offset + 16-bit segment) huge - The same asfar, but the compiler generates code to automatically manage the segment when doing pointer arithmetic. (This is slow, but can convenient, because it ...


36

They both shared the same memory so it didn't really forward instructions. The Z80 card stopped the 6502 running using the DMA signals and the system swapped between the two by writing to $CN00 where N is the slot number. Since the memory was shared the Z80 stuffed some values (A,X,Y,P) into the 6502 zero page ($F045 and up from the Z80 side) stored the ...


32

I’m aware of three main techniques used to exit protected mode on 286s; they all involve resetting the CPU, they vary on how that is done: using the keyboard controller (which IBM endowed with the ability to reset the CPU); using a chipset-specific “fast reset”; using a triple fault. There’s a detailed discussion of the first and last approaches on Robert ...


30

No, there is no simple one-to-one mapping for the pins. (Bolded signal names will be active-low.) For example, while the 286 has two physical pins for interrupts (INTR and NMI), 68000 has three (IPL0, IPL1 and IPL2), encoding a total of 7 interrupt levels. So the interrupts are handled differently, and also the signaling for acknowledging an interrupt at ...


28

My guess is that it was merely a design decision based upon the assumption that once a protected mode OS is started, there is no need to go back. Most microprocessors at that time already booted in its most privileged mode and had at least two levels of protection. The 80286 had to boot in real mode to keep compatibility with DOS and I think they thought DOS ...


17

This was intentional so that the CPU would support secure operating systems. In a secure operating system with rigorous memory access protections you could not allow any software - user or kernel extension or driver - to switch back to the full freedom of real mode. They had a lot of interesting memory management hardware on the '286: rings and call gates - ...


17

OS/2 supported “huge memory” on 286s. The New Executable format used for 16-bit OS/2 executables (and 16-bit Windows executables) supports multiple segments. At runtime, using the DosAllocHuge function, programs could allocate more than 64KiB of memory at a time, and would get a sequence of segment selectors which could be used to easily access all the ...


16

Most obvious question first: why not puting itn on a ISA Card and take over the bus instead? Given, there would be still some work to be done after asking for DMA and pulling /MASTER, but way less than emulating a totally different CPU protocoll. More like adapting to a weired memory subsystem. But for your points First, most obviously, they are ...


14

The 80286 has a maximum power dissipation of 3.3W and an operating range of up to 70°C. Unless you want to operate near that point, no heat sink is needed. The ICs surface is alreaady way too large. Beyond that it falls into the same class as iluminated cables and coloured ribbons. Not needed but doesn't do harm either (if done properly). From a historic ...


14

That Conner CP-343 drive appears to be a special snowflake, but it's not. It's actually a standard IDE drive, with one exception. That 20-pin interface you're looking at isn't the IDE connector; it's the connector between the drive mechanicals and the controller board that would normally be mounted to the bottom of the drive. Why it's not affixed to the ...


13

There are 386 real-mode emulators for 286s, such as Eko Priono’s EMU386; but they relied on one important feature which 8086s don’t have, the invalid instruction exception. Whenever a 286 attempts to run an invalid instruction, it traps, and a handler can be put in place to emulate the instruction (if it really is a “missing” instruction from a later ...


12

TL;DR: this longish answer address the "mystic" property of the question; i.e., the sense of wonder about how this could be possible; not the actual workings of the specific components. The gory details have been given in other answers, but here is a broader outlook on the issue: Remember that in that time, computers (certainly home computers) were, ...


12

That's a lot of parts for a single question. •what conventions did programmers employ to deal with segmentation? •what extensions exist for common programming languages to accommodate the segmented address space? These seem to be related. Compilers use memory models that make it transparent. The models have names like "tiny", "compact", "large", ...


12

According to an Intel document describing opcodes which don’t result in exception 6, The 0F1H opcode is a prefix which performs no function. It counts like any other prefix towards the maximum instruction length. No restrictions apply to its execution. The same document mentions explicitly when opcodes are aliases for others. I interpret the above as ...


11

I don’t recall SPARC systems having separate sockets for discrete FPUs; in particular, the Weitek SPARC POWER µP was a replacement SPARC CPU which derived much of its speed benefit from doubling its internal clock. On the x86 FPU side of things, quite a few different companies produced FPUs: Intel of course, AMD, IIT, Cyrix, Chips & Technologies... Many ...


11

PC Magazine 11/1984 was first reporting about the PC/AT 5170. They quote a price tag of 3800 USD for the low end configuration with 256 KiB and 5800 USD for the high end configuration with 512 KiB RAM and 20 MiB HDD. PC clone manufactures to produce 80286 based AT compatibles would have taken at least until 1985. You can try to find the first ads in PC ...


11

Actually this is a lot easier than I thought, after trying to link to another MSW note, I found it in the Intel Instruction Set: Machine Status Word (286+ only). The machine status word seems to be a predecessor to CR0, and protected mode was set in first bit. Of note, you can't return from Protected Mode on the 286. MSW - Machine Status Word (286+ only) ...


9

Well, one of the first will be for sure Intels System 310/286. According to the CHM this would be 1981, but I think it was rather 1982/83 - that would also fit the original flyer. It's a Multibus system using the iSBC 286/10 single board computer running Xenix. The board was also used by several other manufacturers for early 286 based Unix sytems and real ...


9

Yes, there were 16-bit ISA cards which used the extra address lines; for example IBM’s various memory expansion options, most of which could be configured to provide extended memory beyond 1MiB. You can see the address lines referenced in the corresponding schematics, e.g. for the 512KiB/2MiB expansion board. (The PC AT didn’t have SIMM sockets on the ...


9

The trick is that resetting the CPU leaves the RAM intact (unless the system designers have done something that will clear some or all RAM on a reset). So if you leave appropriate information in the RAM to be read by the (real-mode) startup code, it can detect that before the reset a "message" was left to it to do whatever needs to be done in real mode ...


9

The 80287 (and 80187) were functionally identical to the original 8087 coprocessor, just with different external interfaces to match their companion CPUs. The 80387 (also produced as an 80287XL) was the first Intel x87-family FPU to introduce full IEEE-754 compatibility, and this involved some changes to the handling of infinities, Not-a-Numbers (NaNs) and ...


8

There are quite a few 286 chipsets which can be programmed to provide shadow RAM in the upper memory area in such a way that it can be re-used as UMBs. The most comprehensive list I know of is the list given in the CHIPSET.DOC file in The Last Byte Memory Manager. This includes the Suntac ST62C202 and ST62C251, which can provide 128 KiB of shadow RAM (at ...


8

While it is officially documented as "a prefix which performs no function", a thread on the vcfed.org forums has discovered it is an ICE-mode prefix that forces the instruction's memory access to be performed using the normal bus pins instead of the extra pins normally used by the bond-out version of the 286.


8

Have you ever thought of changing the 8088 in your PC to a NEC V20 (uPD70108)? The V20 is basically a 80186/286 EU with an 8088 BU. This offers all the 'new' real mode instructions (*1) you need, while still being pin-compatible with the 8088. And in addition you'll get some 30% sped up as well - quite handy, isn't it? Using a V20 would remove all need to ...


7

When was the 286 first available for purchase by end users Well, this of course depends a lot on the values of 'Available for Purchase' and 'End User'. Is the question about the chip, boards with a 286, or polished turnkey systems including some IBM compatibility? If it's about general availability of working boards, it may be as early as late 1982/early ...


6

Warning about USB to IDE converters and early (before 1995 or so) IDE drives: Those USB adaptors will kill most early IDE drives, I don't know if that's the only reason but early drives used ALE on PIN 28 (goes to ISA BUS ADDRESS LATCH ENABLE) then it was redefined to SPSYNC:CSEL (Spindle synchronization/cable select) and some drives support SPSYNC but not ...


6

Nice piece! Those days such boards were designed for specific chassis, with additional keys and LEDs like Turbo. Here're some manuals: HT-286 - the one similar you found, but it is not yours. This Super-286 seems the one you need though.


6

In general, different CPUs don't use the same bus protocol. Why not? Sure, different manufacturers defined different bus designs - but more often than not, used them across various CPUs and CPU families. A 16-bit CPU would not in general be expected to use the same protocol as an 8-bit CPU. Again, why not? The number of data lines doesn't inherently ask ...


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