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51

LOADALL is an undocumented instruction available on the 80286, 80386 and some 486 clones. It provides a means to load all the CPU's registers in one operation, including normally-inaccessible registers (descriptor caches). Its significance is that it allows extended memory to be accessed on a 286 without switching to protected mode. On a 8086, memory is ...


38

What it boils down to is that, unlike in a flat addressing model, there are multiple types of pointers: near - 16-bit (16-bit offset only.) far - 32-bit (16-bit offset + 16-bit segment) huge - The same asfar, but the compiler generates code to automatically manage the segment when doing pointer arithmetic. (This is slow, but can convenient, because it ...


35

They both shared the same memory so it didn't really forward instructions. The Z80 card stopped the 6502 running using the DMA signals and the system swapped between the two by writing to $CN00 where N is the slot number. Since the memory was shared the Z80 stuffed some values (A,X,Y,P) into the 6502 zero page ($F045 and up from the Z80 side) stored the ...


31

I’m aware of three main techniques used to exit protected mode on 286s; they all involve resetting the CPU, they vary on how that is done: using the keyboard controller (which IBM endowed with the ability to reset the CPU); using a chipset-specific “fast reset”; using a triple fault. There’s a detailed discussion of the first and last approaches on Robert ...


29

No, there is no simple one-to-one mapping for the pins. (Bolded signal names will be active-low.) For example, while the 286 has two physical pins for interrupts (INTR and NMI), 68000 has three (IPL0, IPL1 and IPL2), encoding a total of 7 interrupt levels. So the interrupts are handled differently, and also the signaling for acknowledging an interrupt at ...


28

My guess is that it was merely a design decision based upon the assumption that once a protected mode OS is started, there is no need to go back. Most microprocessors at that time already booted in its most privileged mode and had at least two levels of protection. The 80286 had to boot in real mode to keep compatibility with DOS and I think they thought DOS ...


17

OS/2 supported “huge memory” on 286s. The New Executable format used for 16-bit OS/2 executables (and 16-bit Windows executables) supports multiple segments. At runtime, using the DosAllocHuge function, programs could allocate more than 64KiB of memory at a time, and would get a sequence of segment selectors which could be used to easily access all the ...


16

This was intentional so that the CPU would support secure operating systems. In a secure operating system with rigorous memory access protections you could not allow any software - user or kernel extension or driver - to switch back to the full freedom of real mode. They had a lot of interesting memory management hardware on the '286: rings and call gates - ...


16

Most obvious question first: why not puting itn on a ISA Card and take over the bus instead? Given, there would be still some work to be done after asking for DMA and pulling /MASTER, but way less than emulating a totally different CPU protocoll. More like adapting to a weired memory subsystem. But for your points First, most obviously, they are ...


14

The 80286 has a maximum power dissipation of 3.3W and an operating range of up to 70°C. Unless you want to operate near that point, no heat sink is needed. The ICs surface is alreaady way too large. Beyond that it falls into the same class as iluminated cables and coloured ribbons. Not needed but doesn't do harm either (if done properly). From a historic ...


12

That's a lot of parts for a single question. •what conventions did programmers employ to deal with segmentation? •what extensions exist for common programming languages to accommodate the segmented address space? These seem to be related. Compilers use memory models that make it transparent. The models have names like "tiny", "compact", "large", ...


12

TL;DR: this longish answer address the "mystic" property of the question; i.e., the sense of wonder about how this could be possible; not the actual workings of the specific components. The gory details have been given in other answers, but here is a broader outlook on the issue: Remember that in that time, computers (certainly home computers) were, ...


12

According to an Intel document describing opcodes which don’t result in exception 6, The 0F1H opcode is a prefix which performs no function. It counts like any other prefix towards the maximum instruction length. No restrictions apply to its execution. The same document mentions explicitly when opcodes are aliases for others. I interpret the above as ...


10

That Conner CP-343 drive appears to be a special snowflake, but its not. Its actually a standard IDE drive, with one exception. That 20-pin interface you're looking at isn't the IDE connector, its the connector between the drive mechanicals and the controller board that would normally be mounted to the bottom of the drive. Why its not affixed to the ...


10

I don’t recall SPARC systems having separate sockets for discrete FPUs; in particular, the Weitek SPARC POWER µP was a replacement SPARC CPU which derived much of its speed benefit from doubling its internal clock. On the x86 FPU side of things, quite a few different companies produced FPUs: Intel of course, AMD, IIT, Cyrix, Chips & Technologies... Many ...


10

Actually this is a lot easier than I thought, after trying to link to another MSW note, I found it in the Intel Instruction Set: Machine Status Word (286+ only). The machine status word seems to be a predecessor to CR0, and protected mode was set in first bit. Of note, you can't return from Protected Mode on the 286. MSW - Machine Status Word (286+ only) ...


9

PC Magazine 11/1984 was first reporting about the PC/AT 5170. They quote a price tag of 3800 USD for the low end configuration with 256 KiB and 5800 USD for the high end configuration with 512 KiB RAM and 20 MiB HDD. PC clone manufactures to produce 80286 based AT compatibles would have taken at least until 1985. You can try to find the first ads in PC ...


9

The trick is that resetting the CPU leaves the RAM intact (unless the system designers have done something that will clear some or all RAM on a reset). So if you leave appropriate information in the RAM to be read by the (real-mode) startup code, it can detect that before the reset a "message" was left to it to do whatever needs to be done in real mode ...


8

Well, one of the first will be for sure Intels System 310/286. According to the CHM this would be 1981, but I think it was rather 1982/83 - that would also fit the original flyer. It's a Multibus system using the iSBC 286/10 single board computer running Xenix. The board was also used by several other manufacturers for early 286 based Unix sytems and real ...


8

Yes, there were 16-bit ISA cards which used the extra address lines; for example IBM’s various memory expansion options, most of which could be configured to provide extended memory beyond 1MiB. You can see the address lines referenced in the corresponding schematics, e.g. for the 512KiB/2MiB expansion board. (The PC AT didn’t have SIMM sockets on the ...


8

While it is officially documented as "a prefix which performs no function", a thread on the vcfed.org forums has discovered it is an ICE-mode prefix that forces the instruction's memory access to be performed using the normal bus pins instead of the extra pins normally used by the bond-out version of the 286.


7

There are quite a few 286 chipsets which can be programmed to provide shadow RAM in the upper memory area in such a way that it can be re-used as UMBs. The most comprehensive list I know of is the list given in the CHIPSET.DOC file in The Last Byte Memory Manager. This includes the Suntac ST62C202 and ST62C251, which can provide 128 KiB of shadow RAM (at ...


6

Nice piece! Those days such boards were designed for specific chassis, with additional keys and LEDs like Turbo. Here're some manuals: HT-286 - the one similar you found, but it is not yours. This Super-286 seems the one you need though.


5

Just speculating here, but it might have been a product decision to encourage writing code for protected mode. It's also possible it was a combination of technical difficulties and product priorities. The CPU is put into protected mode by setting the PE bit in MSW using the LMSW or LOADALL instructions. Clearing the PE bit has no effect using either of ...


5

In terms of operating system design concepts like memory models are a bit of a red herring. Operating systems like MS-DOS and 16-bit Windows didn't care about these things. They provided a mechanism to load executables and provided an API that those executables could use to invoke system services. How programs dealt with segmentation was left to the ...


5

One thing that hasn't been addressed yet: relocation. It's actually easier when you're using a segment:offset architecture. The segment registers take care of most of the work for you. A dos .COM file didn't have any relocation capability--it's simply a memory image, nothing more. It would be loaded wherever the operating system felt like loading it, ...


5

There is some information about LOADALL on Wikipedia, and several OS-related sites, but the first time I (and I guess many others) knew about LOADALL is from this documented from Terrance E. Hodgins. I haven't found any copy to this document online (well, a simple Google search with the words Terrance E. Hodgings or Hyper-Space Navigator's guide doesn't get ...


5

When was the 286 first available for purchase by end users Well, this of course depends a lot on the values of 'Available for Purchase' and 'End User'. Is the question about the chip, boards with a 286, or polished turnkey systems including some IBM compatibility? If it's about general availability of working boards, it may be as early as late 1982/early ...


5

70 or 80ns SIMMs are supported, and are in fact required if you wish to run your system with no wait states. 120ns SIMMs would require one wait state. Even though your motherboard manual doesn’t mention memory speeds, the fact that is supports disabling wait states indicates that it works fine with faster memory. (AFAIK faster memory shouldn’t cause issues ...


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