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84 votes
Accepted

Intel CPU bug in the 90s

I suspect your teacher was referring to the FDIV Pentium bug, which led to a large outcry in the media at the time and for which Intel issued a recall. This bug caused floating-point division to ...
Stephen Kitt's user avatar
69 votes

Which "very esoteric processor instructions" are used by OS/2?

As far as I’m aware the difficulty in virtualising OS/2 isn’t due to esoteric processor instructions, but rather esoteric processor features. Specifically, OS/2 uses all the protected mode features ...
Stephen Kitt's user avatar
61 votes

Can an x86 CPU running in real mode be considered to be basically an 8086 CPU?

An x86 CPU running in real mode is intended to be backwards-compatible with an 8086 or 8088, but there do end up being a number of differences, for example: newer CPUs run faster (in general); newer ...
Stephen Kitt's user avatar
61 votes

What was the last x86 CPU that did not have the x87 floating-point unit built in?

As far as I’m aware, the last FPU-less x86-compatible CPU which could still be considered general-purpose is the Vortex86SX, released in 2007 and still available now. This is a Pentium-class CPU, ...
Stephen Kitt's user avatar
56 votes
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The start of x86: Intel 8080 vs Intel 8086?

8086 was designed to make asm source porting from 8080 easy (not the other direction). It is not binary compatible with 8080, and not source-compatible either. 8080 is not an x86 CPU. 8080 is a ...
Peter Cordes's user avatar
  • 3,197
50 votes
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Can x86 processors run 8-bit applications?

There are several aspects to consider to answer your question. The x86 architecture is backwards-compatible with the first CPU of the line, the 8086 (and its sibling, the 8088). What this means is ...
Stephen Kitt's user avatar
48 votes

What does the "x" in "x86" represent?

The term x86 is shorthand for 80x86, which was used to refer to any member of the family 8086 (and also, incidently, 8088), 80186, 80286, etc. Things have since gotten a bit muddled by the fact that ...
supercat's user avatar
  • 36.5k
48 votes

What was the last x86 processor that didn't have a microcode layer?

The original 8086 was microcoded; x86 has never been hard-wired. The P6 microarchitecture, first seen in the Pentium Pro, was the first Intel design to buffer a RISC-esque translation of the x86 ...
Tommy's user avatar
  • 37.3k
47 votes
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What are the "virtual machines" that were running on 80386 and later x86 CPUs before full hardware virtualization?

I would think the articles you've read were most likely about the Virtual 8086 Mode introduced with the 386. Here a host OS (running at privilege 0) would create a standard protected process, but mark ...
Raffzahn's user avatar
  • 224k
45 votes

Why can't I invoke the next interrupt service by incrementing the AX register after calling the same interrupt?

When calling the mouse driver interrupt with AX = 0, it returns 0xFFFF in AX if a mouse driver is installed. So if it is installed, the code with INC AX will increment AX back to 0 and then it will ...
Justme's user avatar
  • 32.8k
40 votes

What are the "virtual machines" that were running on 80386 and later x86 CPUs before full hardware virtualization?

"Virtual machine" has a long and varied history, not always meaning exactly what it means today. Early designers of timesharing systems viewed what they were providing to their users was a ...
dave's user avatar
  • 35.7k
40 votes

Did any x86 CPU optionally trap unaligned access?

Not on a 386, but all x86 processors from the 486 forward support an alignment checking mode, which does basically what you describe: it causes an exception on any unaligned access from ring 3. See ...
user24811's user avatar
  • 1,617
39 votes

What does the "x" in "x86" represent?

x is meant as wildcard, so this represents all CPUs able to run 8086 compatible code.
Raffzahn's user avatar
  • 224k
37 votes

How does the ‘real mode flat model’ work?

I’m assuming you’re asking about x86 processors, not the older 8-bit CPUs. Real mode is always segmented, and everything (CPU, operating system, programs, even peripherals on the CPU bus) has access ...
Stephen Kitt's user avatar
35 votes

Why did x86 support self-modifying code in the 80s and 90s?

Raffzahn has the main idea: once self-modifying code had been supported in the past, it had to continue to be supported in perpetuity. But just to go back a little further, https://stackoverflow.com/...
Nate Eldredge's user avatar
32 votes
Accepted

Detecting the external x87 FPU

The documented way to detect an x87 FPU is to attempt to initialise it, and then read its control word (FPU_STATUS must be set to some non-zero value first): FNINIT FNSTSW WORD PTR [FPU_STATUS] This ...
Stephen Kitt's user avatar
32 votes
Accepted

Why was there a need for separate I/O address space in addition to a memory address space already?

do not mention why or why not a single memory address space could be used from the beginning. Simply because a dedicated I/O space simplifies system design. It may be assumed that you're asking ...
Raffzahn's user avatar
  • 224k
32 votes

What was the last x86 processor that didn't have a microcode layer?

All x86 CPUs have always used microcode. Since the i486, the simplest and most used instructions are directly decoded without passing through the microcode ROM, which would have incurred additional ...
Grabul's user avatar
  • 3,647
31 votes

Intel CPU bug in the 90s

Stephen Kitt has already provided a good answer regarding the FDIV bug. I'll fill in some details about Intel employing logicians: Because of this bug, Intel had to replace a lot of processors, which ...
Bagnus's user avatar
  • 411
31 votes
Accepted

How did 16-bit MS-DOS programs use a large (> 64KB) stack?

They simply did not use a large stack. If you look at the standard memory models for the x86, there was a single stack segment in all of them (which was even shared with other segments in the smaller ...
dirkt's user avatar
  • 27.8k
30 votes

Can x86 processors run 8-bit applications?

The 8086 is source-code compatible with the 8080 (the other way around is not true). This means that most assembly code written for the 8080 can be assembled so that 8086 instructions are emitted. The ...
mcleod_ideafix's user avatar
30 votes

Why can't I invoke the next interrupt service by incrementing the AX register after calling the same interrupt?

Calling an interrupt service is more like invoking a system call than it is like writing to a memory-mapped register. That is, when you invoke a software interrupt, there is no guarantee that the ...
user3840170's user avatar
  • 23.1k
29 votes
Accepted

How can a 32-bit x86 CPU start with reset vector 0xFFFFFFF0 even though it starts in 16-bit real mode?

When x86 boots, it's not strictly in classic real mode, it's in "unreal" mode, with CS.base = 0xFFFF0000 and CS.limit = 64K. On 286 and later, memory addressing doesn't use the segment ...
Peter Cordes's user avatar
  • 3,197
28 votes
Accepted

How were the test registers used on the i386 and the i486?

The 486 test registers are described in the i486 Processor Programmer’s Reference Manual, starting on page 10-8. The 386 test registers are a subset. Registers TR6 and TR7 provide access to the TLB. ...
Stephen Kitt's user avatar
28 votes

In x86 real mode, how does BIOS know what hardware is present?

The IBM PC design makes a provision for option ROMs, which allow expansion cards to patch extensions into the BIOS. That's how you get things like the IBM EGA card retrofitting new int 10h services ...
ssokolow's user avatar
  • 7,065
28 votes
Accepted

Did any software attempt to perform 8086 emulation on the 80286 using LOADALL, in the vein of the later virtual 8086 mode of the 80386?

I believe what you are describing was in fact done. Concurrent DOS for the 286 could multitask DOS programs in protected mode. See the Wikipedia article on Multiuser DOS as well as DOS VMs. The ...
RETRAC's user avatar
  • 13.7k
28 votes
Accepted

Detecting the version of i486 CPU

The most comprehensive pre-CPUID x86 CPU detection code I’m aware of is in TMi0SDGL (Too Much in One So Don’t Get Lost). It includes source code. It will use model-specific MSRs, BIOS services etc. to ...
Stephen Kitt's user avatar
28 votes

Were there any PCs using the i376?

To complement John Dallman’s answer, regarding your last question: If no, why did the BIOS authors reserve such a code for a CPU clearly targetted towards a different market? The BIOS authors didn’t ...
Stephen Kitt's user avatar
27 votes
Accepted

Why does the x86 not have an instruction to obtain its instruction pointer?

As Thorbjørn Ravn Andersen already put it nicely: What would you need it for? There is almost no practical (*1) need to obtain the PC address at runtime (*2) - it's a value to be obtained during ...
Raffzahn's user avatar
  • 224k

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