Hot answers tagged

75

I suspect your teacher was referring to the FDIV Pentium bug, which led to a large outcry in the media at the time and for which Intel issued a recall. This bug caused floating-point division to return incorrect results in some cases. It didn’t affect only FDIV, some related instructions were affected: the other division and remainder instructions, and FPTAN ...


67

As far as I’m aware the difficulty in virtualising OS/2 isn’t due to esoteric processor instructions, but rather esoteric processor features. Specifically, OS/2 uses all the protected mode features available on 286 (OS/2 1.x) and 386 (OS/2 2.0 and later) PCs: segment limits, paging, protection rings... The latter has commonly been given as the main ...


57

An x86 CPU running in real mode is intended to be backwards-compatible with an 8086 or 8088, but there do end up being a number of differences, for example: newer CPUs run faster (in general); newer CPUs add new instructions (and, with the 386, new registers, since the 32-bit registers can be used in real mode); 286 and later CPUs add more address lines, ...


55

As far as I’m aware, the last FPU-less x86-compatible CPU which could still be considered general-purpose is the Vortex86SX, released in 2007 and still available now. This is a Pentium-class CPU, capable of running any Pentium code which doesn’t require an FPU. It is targeted at embedded applications, with up to 512 MiB of RAM, and includes a PCI bus, USB, ...


52

8086 was designed to make asm source porting from 8080 easy (not the other direction). It is not binary compatible with 8080, and not source-compatible either. 8080 is not an x86 CPU. 8080 is a more distant ancestor that had some influence on the design of 8086, but it's not the same architecture. As an analogy, all x86 CPUs are the same genus but ...


50

There are several aspects to consider to answer your question. The x86 architecture is backwards-compatible with the first CPU of the line, the 8086 (and its sibling, the 8088). What this means is that, when a modern Intel (or AMD) processor boots up, it starts in a mode which is compatible with the 8086 — if the motherboard's BIOS support is good enough, ...


48

The term x86 is shorthand for 80x86, which was used to refer to any member of the family 8086 (and also, incidently, 8088), 80186, 80286, etc. Things have since gotten a bit muddled by the fact that while an 80386 had a mode that was compatible with the old architecture, it also introduced some fundamentally new ways of doing things which were shared by the ...


44

When calling the mouse driver interrupt with AX = 0, it returns 0xFFFF in AX if a mouse driver is installed. So if it is installed, the code with INC AX will increment AX back to 0 and then it will just reset the mouse driver a second time. It is very typical that interfaces that use software interrupts give you back a status code in AL or AX, so this is no ...


39

x is meant as wildcard, so this represents all CPUs able to run 8086 compatible code.


35

I’m assuming you’re asking about x86 processors, not the older 8-bit CPUs. Real mode is always segmented, and everything (CPU, operating system, programs, even peripherals on the CPU bus) has access to all the system’s address space up to just over 1 MiB (1 MiB strictly before the 286). You can write programs without paying attention to segments, and you’ll ...


31

The documented way to detect an x87 FPU is to attempt to initialise it, and then read its control word (FPU_STATUS must be set to some non-zero value first): FNINIT FNSTSW WORD PTR [FPU_STATUS] This uses the non-waiting variants, otherwise the CPU will wait for a non-existent FPU to respond. If the status word is not 0 after this, no FPU is installed — the ...


30

The 8086 is source-code compatible with the 8080 (the other way around is not true). This means that most assembly code written for the 8080 can be assembled so that 8086 instructions are emitted. The only exceptions would be self-modifying code or code that relies on interrupts, which are handled differently on both processors. In fact, some assemblers, ...


28

Stephen Kitt has already provided a good answer regarding the FDIV bug. I'll fill in some details about Intel employing logicians: Because of this bug, Intel had to replace a lot of processors, which was very expensive. Not wanting to repeat this, they hired a number of computer scientists with background in formal logic to prove the correctness of ...


27

Calling an interrupt service is more like invoking a system call than it is like writing to a memory-mapped register. That is, when you invoke a software interrupt, there is no guarantee that the register values will be the same that they have been before the interrupt call. In fact, most of the time, they will not be, unless the interrupt service routine ...


26

Here is a reference to BIOS beep codes. For American Megatrends, look under AMI. 3 beeps means the low 64K failed - a very basic test - which probably means the RAM isn't working at all. You should first check whether the RAM is compatible with your machine. At that time, there was a lot of variation - 5V vs 3.3V, 30-pin vs 72-pin, EDO vs FPM, not to ...


25

To supplement @PeterCordes's excellent answer, I thought it would be worth going into the details of exactly how close to source code compatible the two processors are -- for example, how easy would it be to use textual substitutions (e.g. macros) to automatically translate 8080 code to 8086 code, and what the limitations would be. The first point would be ...


23

A few 16-bit processors can run 8-bit code: the NEC V20 series. The V20 and V30 are the ones you might encounter in a PC. The V20 is a pin-compatible substitute for the 8088, and the V30 for the 8086. These processors have a BRKEM instruction (in Intel's notation it would most likely be 'INTEM') which switches to the 8080 instruction set and jumps to an ...


22

The 486 test registers are described in the i486 Processor Programmer’s Reference Manual, starting on page 10-8. The 386 test registers are a subset. Registers TR6 and TR7 provide access to the TLB. They are defined as follows: TR6: 31-12 11 10-9 8-7 6-5 4-1 0 Linear address Valid Dirty User/supervisor Read/write Reserved (0) Command TR7: 31-12 11 10 9-...


20

Preface The question is a bit unclear(*1) about the margins set regarding: Must it be a single motherboard or do separate assemblies qualify? Must it be PC-compatible or does any x86 system qualify? Must the board have been available separately (to the general public) or do complete assembled systems qualify? So answers do vary a lot depending on what ...


20

Intel had a rather complex bunch of hardware to compute a floating-point quotient in a way that yielded two bits per iteration, which required having a rather large table listing all the combinations of bit patterns where part of the quotient should be 11 [rather than listing all patterns individually, the table would have had entries where each bit may be 0,...


18

There is no such thing as an 8-bit application for the x86 architecture, because the x86 architecture has always been at least 16-bit right from the first generation of x86 processors. The x86 does allow access to 8-bit registers, but the code is still 16-bit and the processor is still running as a 16-bit processor. Of course, if you're trying to run 8-bit ...


18

DOS programs always start in real mode (or an emulation thereof), so it’s best to start disassembling them assuming that. When disassembling, you should assume real mode, with 16-bit data and 16-bit addresses, until the code you’re disassembling changes that. The DOS-based disassemblers I’ve used generally know about the executable formats involved, and don’...


18

Full disclosure: I worked on the x87 FPU of a 486-class CPU at a math-coprocessor company in the early 1990s and thereafter worked at AMD, where I was on the 3DNow! design team and the design team for the FPU of the AMD Athlon processor (also known as K7). The x87 FPU never acquired a flush-to-zero mode. In fact, denormal support was one of the major ...


18

The difference is that the latter appeared in DOS 2.0. MS-DOS 1.x was pretty much a rebranded version of Seattle Computer Products’ 86-DOS (initially named QDOS), which in turn was heavily inspired by CP/M. One of the design goals of 86-DOS has been to maintain a certain level of compatibility with CP/M-80: specifically, to be able to port CP/M software to ...


18

I have used these passive PCI risers quite a lot and some of them need their "fingers" to be cleaned with something like isopropanol before they work properly. Especially on the top photo the fingers on the red riser don't all look clean enough.


17

All Intel x86 CPUs since the 80486 line have included floating point instructions, i.e. everything from the Pentium* onward. So the last Intel processor to lack an on-board floating-point unit (FPU) was the 80486SX (and the embedded 80486GX). Other manufacturers, who made 486-compatible processors, continued making non-FPU chips, aiming for the budget ...


17

The XMS specification is still accurate: functions 0x10 and 0x11 provide access to UMBs. However, the specification doesn’t decide where those functions are implemented. On its own, HIMEM.SYS does indeed only provide access to memory above 1MiB, i.e. the HMA (so it also controls the A20 line) and extended memory (which it makes available as XMS). If you only ...


16

Here's a manual for CROS and one for the C500C robot controller. It seems clear that the bytecode files are compiled from the RAPL-3 programming language (no filename extension for binaries, .r3 for source files, .v3 for "variables files". There's a manual for the language here and for the development tools, which run on Windows, here. The manual for ...


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