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56

An x86 CPU running in real mode is intended to be backwards-compatible with an 8086 or 8088, but there do end up being a number of differences, for example: newer CPUs run faster (in general); newer CPUs add new instructions (and, with the 386, new registers, since the 32-bit registers can be used in real mode); 286 and later CPUs add more address lines, ...


54

As far as I’m aware, the last FPU-less x86-compatible CPU which could still be considered general-purpose is the Vortex86SX, released in 2007 and still available now. This is a Pentium-class CPU, capable of running any Pentium code which doesn’t require an FPU. It is targeted at embedded applications, with up to 512 MiB of RAM, and includes a PCI bus, USB, ...


51

Video game hardware, whether for home consoles or arcade machines, is designed pretty much from scratch. Hardware designers have pretty much free rein on choosing what CPU to use, basing their choice on factors like cost and ease of programming. The Intel 8086, quite frankly, was a poorly designed processor and was never well regarded. While you could ...


48

The term x86 is shorthand for 80x86, which was used to refer to any member of the family 8086 (and also, incidently, 8088), 80186, 80286, etc. Things have since gotten a bit muddled by the fact that while an 80386 had a mode that was compatible with the old architecture, it also introduced some fundamentally new ways of doing things which were shared by the ...


47

There are several aspects to consider to answer your question. The x86 architecture is backwards-compatible with the first CPU of the line, the 8086 (and its sibling, the 8088). What this means is that, when a modern Intel (or AMD) processor boots up, it starts in a mode which is compatible with the 8086 — if the motherboard's BIOS support is good enough, ...


46

8086 was designed to make asm source porting from 8080 easy (not the other direction). It is not binary compatible with 8080, and not source-compatible either. 8080 is not an x86 CPU. 8080 is a more distant ancestor that had some influence on the design of 8086, but it's not the same architecture. As an analogy, all x86 CPUs are the same genus but ...


38

x is meant as wildcard, so this represents all CPUs able to run 8086 compatible code.


30

The 8086 is source-code compatible with the 8080 (the other way around is not true). This means that most assembly code written for the 8080 can be assembled so that 8086 instructions are emitted. The only exceptions would be self-modifying code or code that relies on interrupts, which are handled differently on both processors. In fact, some assemblers, ...


26

Here is a reference to BIOS beep codes. For American Megatrends, look under AMI. 3 beeps means the low 64K failed - a very basic test - which probably means the RAM isn't working at all. You should first check whether the RAM is compatible with your machine. At that time, there was a lot of variation - 5V vs 3.3V, 30-pin vs 72-pin, EDO vs FPM, not to ...


23

To supplement @PeterCordes's excellent answer, I thought it would be worth going into the details of exactly how close to source code compatible the two processors are -- for example, how easy would it be to use textual substitutions (e.g. macros) to automatically translate 8080 code to 8086 code, and what the limitations would be. The first point would be ...


22

A few 16-bit processors can run 8-bit code: the NEC V20 series. The V20 and V30 are the ones you might encounter in a PC. The V20 is a pin-compatible substitute for the 8088, and the V30 for the 8086. These processors have a BRKEM instruction (in Intel's notation it would most likely be 'INTEM') which switches to the 8080 instruction set and jumps to an ...


18

Preface The question is a bit unclear(*1) about the margins set regarding: Must it be a single motherboard or do separate assemblies qualify? Must it be PC-compatible or does any x86 system qualify? Must the board have been available separately (to the general public) or do complete assembled systems qualify? So answers do vary a lot depending on what ...


17

All Intel x86 CPUs since the 80486 line have included floating point instructions, i.e. everything from the Pentium* onward. So the last Intel processor to lack an on-board floating-point unit (FPU) was the 80486SX (and the embedded 80486GX). Other manufacturers, who made 486-compatible processors, continued making non-FPU chips, aiming for the budget ...


17

Full disclosure: I worked on the x87 FPU of a 486-class CPU at a math-coprocessor company in the early 1990s and thereafter worked at AMD, where I was on the 3DNow! design team and the design team for the FPU of the AMD Athlon processor (also known as K7). The x87 FPU never acquired a flush-to-zero mode. In fact, denormal support was one of the major ...


16

There is no such thing as an 8-bit application for the x86 architecture, because the x86 architecture has always been at least 16-bit right from the first generation of x86 processors. The x86 does allow access to 8-bit registers, but the code is still 16-bit and the processor is still running as a 16-bit processor. Of course, if you're trying to run 8-bit ...


15

The XMS specification is still accurate: functions 0x10 and 0x11 provide access to UMBs. However, the specification doesn’t decide where those functions are implemented. On its own, HIMEM.SYS does indeed only provide access to memory above 1MiB, i.e. the HMA (so it also controls the A20 line) and extended memory (which it makes available as XMS). If you ...


15

Here's a manual for CROS and one for the C500C robot controller. It seems clear that the bytecode files are compiled from the RAPL-3 programming language (no filename extension for binaries, .r3 for source files, .v3 for "variables files". There's a manual for the language here and for the development tools, which run on Windows, here. The manual for ...


13

This addressing mode was introduced with the first 32-bit x86 processor, i.e. the 80386. Ref: 80386 Programmer's reference manual sec 2.5.3.2.


13

The 486, introduced in 1989, was the first x86 CPU to include a cache. It added cache-supporting instructions to the x86 ISA such as INVD and WBINVD. The 386 didn’t have an on-board cache, but it could be associated with an 82385 controller to use an external cache. Some later 386-compatible CPUs, such as IBM’s 386SLC, included on-board cache; Intel’s own ...


13

It started out as a single manual covering hard and software, the The 8086 Family User's Manual. Before that there were only data sheets and manuals about single components, software tools and development boards as well as premade components (iSBC computer boards) (*1). After that it became the iAPX 86,88 User's Manual. The 80286 manuals (*2) were the ...


12

Swapping byte lanes on the physical bus would, in any case, only have an effect on naturally aligned data in memory, which happened to be the same width as the bus. Swapping the lanes of a 16-bit bus doesn't solve the problem for 32-bit data, nor on a 32-bit bus for 64-bit or 80-bit data (the latter being associated with floating point). So that is not a ...


11

What exactly does it mean to be a "Pascal machine" in that context? It's close but not really the case. It starts with the term Pascal Machine being misused, as this usually describes a software and/or hardware to interpret p-code; today we would call it bytecode, like the Pascal Microengine or a p-code interpreter. This virtual machine was called by its ...


11

Actually this is a lot easier than I thought, after trying to link to another MSW note, I found it in the Intel Instruction Set: Machine Status Word (286+ only). The machine status word seems to be a predecessor to CR0, and protected mode was set in first bit. Of note, you can't return from Protected Mode on the 286. MSW - Machine Status Word (286+ only) ...


11

If you’re looking specifically for motherboards directly supporting multiple x86 CPUs, in a multiprocessor configuration, and available for purchase outside the system they were designed for, a likely candidate for the first such motherboard is the Gigabyte GA-586ID, which supported two socket 5 Pentium CPUs in an SMP configuration. It was released in 1994. ...


11

Short Answer: Yes. Celeron is a sales name, and does not specify a CPU architecture or instruction set. Having said that, FCOMIP was introduced with the P6 Family, so essentially with the Pentium PRO (for workstation) and Pentium MMX for mainstream machines. IA-32 implementations before these CPUs do not feature this instruction. The first Celeron is ...


10

Note all your references to changing values are below the stack pointer, actually a free space. You are not expected to care about this area (stack grows towards lower addresses), as this is of no concern to your application. Even if your computer is sitting at a debugger prompt and apparently is inactive, it isn't. It constantly runs through interrupt ...


10

Your code is correct; a yellow prompt means that you’re using the red/green/brown palette. However, to get the low intensity variant, you also need to call interrupt 10h service 0Bh with BX set to 0 (black background, low intensity; strictly speaking, you can have any background — the bottom four bits, 3–0 — and the fifth bit, bit 4, controls the intensity; ...


9

iRMX III is a real-time operating system for Intel 80386 and later processors, originally developed by Intel and now maintained by tenAsys. A quick look at the System Call Reference manual reveals that it uses call gates.


9

In modern usage it also means software which only uses the 32-bit architecture of the earlier 80x86 processors, to distinguish it from 64-bit applications. Microsoft uses it that way on 64-bit versions of Windows, which have two separate directories called "Program Files" and "Program Files (x86)." The 32-bit applications will run on 64-bit hardware, but ...


9

Konix Multisystem: 6 MHz 8086 (1989). Sure, it was cancelled just before release, but it got amazing press (I remember Jeff Minter raving about it at Earls Court) and some of it lived on as the (68k based) Atari Jaguar.


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