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I'm trying to learn a bit more about the internal workings of the 6502.

The manual says that the branch instructions do not affect the carry flag. However, my understanding is that some carry handling may be required when adding the relative branch offset to the program counter in order to calculate the branch destination address.

Where is this temporary carry bit stored? Is there a different carry storage (other than the carry flag in the program status register), or maybe the program status register is pushed/pulled to the stack so that it is not affected by this address calculation?

Also, it seems to me the same situation occurs when using the abs,X/Y addressing modes. Is that correct?

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    There is lots of 6502 information at 6502.org.
    – John Dallman
    Commented Jul 17, 2022 at 14:16

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The manual says that the branch instructions do not affect the carry flag. However, my understanding is that some carry handling may be required when adding the relative branch offset to the program counter in order to calculate the branch destination address.

It seems you're mixing up the Carry Flag within the status register with the Carry Output of the ALU.

  • The Carry Output is generated whenever an ALU operation is performend,

but

  • the Carry Flag within the status register is only updated from carry output for certain operations (like mentioned in the manual).

Where is this temporary carry bit stored?

There is no temporary storage - there is only an output at the end of an ALU operation.

  • When the ALU is used to perform an ALU related instruction (ADC/SBC/ROL/ROR/...) the carry output gets copied into the status register.
  • When the ALU is used to calculate an address, carry output is used by the control logic to detect carry has happened, which in turn inserts another cycle to increment the high part by one, which during its execution simply ties carry input to one(*1).

Also, it seems to me the same situation occurs when using the abs,X/Y addressing modes.

The address case happens whenever a page boundary is crossed. Either by a relative branch adding the signed branch offset to PC or by an unsigned indexing operation. Affected addressing modes are

  • Relative
  • Absolute, X
  • Absolute, Y
  • Indirect, Y

As all of them may result in crossing a page as soon as the sum of the lower byte of the address plus the index value exceeds 255 (*2).

X, Indirect, Zero page, X and Zero page, Y are not among them, as here the generated address will simply wrap.

Where to Find It

When looking at Hanson's famous drawing

enter image description here

(Taken from the cleaned up version on his site)

the various connections are well marked:

  • [green] Carry Output, from the ALU, called Carry, is visible at the lower side of the ALU, it creates a signal called ACR
  • [blue] It gets moved into the Carry Flag when the signal ACR/C gets activated by the control logic (the connection of ACR to Cis implied)
  • [red] Carry Input is transferred from control logic to the ALU via the signal I/ADDC
  • [orange] I/ADDC is generated by the control logic either
    • by copying the Carry Flag, in case of an arithmetic operation, or
    • by setting it always to one during the additional cycle of a page crossing to generate an increment (*3), or decrement in case of a relative jump backwards (*4).

*1 - It helps to keep in mind that an operation does not depend on where an information is stored, but that its signification is available when needed. There is no need to hold a dedicated carry flag in case of a high byte correction, as doing so already implies the existence of a previous carry

The best optimization of storage is to not need it..

This might of course be displayed different in a text book :))

*2 - Or goes below zero in case of a branch with negative value.

*3 - This works like any other increment by putting the value to be incremented into the B Input Register, clearing the A Input register (via 0/ADD [yellow]), setting carry (I/ADDC) and selecting the result of an addition as output (SUMS [beige]).

*4 - Detection and execution of a backward branch is a bit more complicated, but essentially the same, so let's spare that for simplicity.

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  • Thanks a lot, very useful info. So I guess, although it is not shown on the drawing, ACR is somehow fed into "Random Control Logic" so that it can influence the control signals. Also, is it possible that using relative addressing mode with a negative offset would cause PCH to actually be decremented?
    – Patrick LeBoutillier
    Commented Jul 18, 2022 at 19:24
  • @PatrickLeBoutillier Yes, as said, it's always going thru the Control - after all, that's where instructions sequencing is supposed to be controlled. And yes, unlike indexing which only works with positive numbers, branches contain signed values and may result in a decrement of PCH. Thus, while working essentially the same, it does take care of the sign bit. I left out these details to keep it somewhat simple. If you're really into further details, a look at the visual 6502 may help - just don't expect it a ride for beginners :))
    – Raffzahn
    Commented Jul 18, 2022 at 20:59
  • Is visual6502.org down? I can't seem to be able to access it for the last couple of days...
    – Patrick LeBoutillier
    Commented Jul 19, 2022 at 21:09
  • Oh, interesting. Well, since all pages as well as the simulator itself is pure web content, Archive.Org's copy might be an acceptable surrogate.
    – Raffzahn
    Commented Jul 19, 2022 at 21:42

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