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32 votes
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Why was there a need for separate I/O address space in addition to a memory address space already?

do not mention why or why not a single memory address space could be used from the beginning. Simply because a dedicated I/O space simplifies system design. It may be assumed that you're asking ...
Raffzahn's user avatar
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22 votes

Why did POKEing ROM addresses mask port writes?

The following is an excerpt from the article César Hernández Bañó and I wrote about the internals of the Inves Spectrum+, exposed after a detailed work of reverse enginnering. First, some background: ...
mcleod_ideafix's user avatar
19 votes
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If a PS/2 device on a 32-bit x86 sends a byte to the IO port 0x60 and you read it, what happens next?

On standard PCs, the main CPU and PS/2 controller use a handshake mechanism in the status register at port 0x64: Main CPU wants to read (probably because it received a keyboard interrupt): Read port ...
tofro's user avatar
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16 votes
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Where is Mike Lesk's (circa 1973) "portable I/O package" for C?

Unless you are an old guy like me, you'll need to run this thru groff -ms unless you know how to decode troff 😄 Mike Lesk's Portable I/O Library
Clem Cole's user avatar
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15 votes

If a PS/2 device on a 32-bit x86 sends a byte to the IO port 0x60 and you read it, what happens next?

There is not only one place in memory, and it is not even memory. The port 0x60 is an IO port in the CPU IO address space for accessing the keyboard controller data port. It is used to access a lot of ...
Justme's user avatar
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13 votes
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Is this a bug or an allowed Pascal behavior?

The ISO 7185 Pascal standard, section 6.4.3.5 "File-types", says (my emphasis): There shall be a file-type that is denoted by the required structured-type-identifier text. The structure of ...
dirkt's user avatar
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13 votes
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Did general purpose I/O controller chips come with fewer than 40 pins?

I nominate the AY-3-8912, which is a sound generator that also has eight programmable input/output pins — set them as input or output, set or get their level — in a 28-pin package. It sits between the ...
Tommy's user avatar
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12 votes

8086 duration of program

On the 8088 and 8086, execution involves two parallel processes--memory access and internal computation--and will be limited by the speed of whichever is slower. Generally, on the 8088 execution ...
supercat's user avatar
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11 votes
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How was character data handled in Fortran IV/66?

Individual characters could be read into integer variables (or elements of integer arrays) using the format specifier A1, manipulated at will, then printed using the A1 format specifier. For example (...
Leo B.'s user avatar
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11 votes

Are there any good resources on emulating/simulating early computing input/output?

You can have a look at how simh, which emulates quite a few computer systems that had punch cards, paper tape, magnetic tape, harddisks, floppy disks, printer and terminals, handle it. Basically most ...
dirkt's user avatar
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10 votes

Did general purpose I/O controller chips come with fewer than 40 pins?

Of course. After all, the number of pins is related to the task at hand. No manufacturer would choose a package with more pins than necessary. Examples of main families are: (Excluding support chips,...
Raffzahn's user avatar
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10 votes

8086 duration of program

I am afraid that the answer is "it could take any time, depending on circumstances and the real WAIT condition". WAIT states have unpredictable length, so there is no exact way to answer ...
Martin Maly's user avatar
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10 votes

Difference between the 8255 and 8042 PPIs

The 8042 is no PIO chip at all, but essentially a (very small) full-blown computer on a chip - a microcontroller. It contains a small amount of RAM (256 Bytes), ROM (4K, One-time-programmable or ...
tofro's user avatar
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9 votes

CONIN (Console In) in CP/M and "old characters" in character latch

Keep in mind that if you call CONIN and there is no NEW character available, it will block until one is available. That's the purpose of the CONST function, it allows an application to check for a ...
jwh20's user avatar
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9 votes
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Maximum speed of serial I/O bit-banged by 8-bit CPU

Well there is no simple answer. If you assume that the CPU runs undisturbed, you can just count the cycles and that's how many systems already handle their tape storage, you just seem to want higher ...
Justme's user avatar
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7 votes
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8086 duration of program

I have the following assembly code for 8086 To start with basic timing for 8086 (*1) in CPU clocks is 21 clock cycles. MOV AL,[BX] (*2) 13 cycles, consisting of 8 cycles for the instruction (MOV ...
Raffzahn's user avatar
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6 votes

Flash border color during Kernal LOAD routine

One could configure the second CIA to trigger an NMI sometime during vertical blank, at a rate precisely equal to the frame rate. If the NMI were something like: bit $dd0d ; Reset NMI inc $...
supercat's user avatar
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6 votes

CONIN (Console In) in CP/M and "old characters" in character latch

I'm very interested in how "old key presses" are handled. Not at all. They are out of scope for CP/M. The CONST and CONIN are direct mapped to respective BIOS functions of the same name (...
Raffzahn's user avatar
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6 votes

How was character data handled in Fortran IV/66?

With respect to this: I've heard anecdotes about working with or modifying FORMAT statements, but I've never seen an example. The FORTRAN IV language for IBM 7090/7094 IBSYS version 13 supported ...
dave's user avatar
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6 votes

Maximum speed of serial I/O bit-banged by 8-bit CPU

Hmm...at least offhand, it seems like you need around 4 instructions per bit and a Z80 needs at least 4 T cycles per instruction. Along with that you need to load the next byte from memory once every ...
Jerry Coffin's user avatar
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6 votes

Maximum speed of serial I/O bit-banged by 8-bit CPU

There are so* many misconceptions in that question, it's hard to know where to start. The issue with IEEE-488 was absolutely nothing to do with it being parallel, and everything to do with it being a ...
Graham's user avatar
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5 votes

How was character data handled in Fortran IV/66?

In FORTRAN 66, you could store up to the word size in characters. For instance, on a 24-bit machine with 6-bit characters INTEGER C1(80), C2(40), C4(20) READ(10,11) (C1(II), II=1, 80) 11 ...
cup's user avatar
  • 2,517
5 votes

Are there any good resources on emulating/simulating early computing input/output?

Peter Onion's Elliott 803 emulator tries to replicate the experience of using an 803 in a 3D, almost VR, setting. Virtual paper tapes are used to load programs and data. Doug W. Jones's Punched Cards ...
scruss's user avatar
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5 votes

Are there any good resources on emulating/simulating early computing input/output?

Not too sure about resources, actually. But, I can walk you through the logic I used when I wrote an (unpublished) emulator for BESK, a machine that had paper tape for input, either in "5-bit ...
Vatine's user avatar
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4 votes

Flash border color during Kernal LOAD routine

I have found on this page a loader that does exactly this. So how does it work? By overriding the ISTOP interrupt handler, which seems to be called by the kernal even during LOAD. One thing I haven't ...
Cactus's user avatar
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4 votes
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READY / WAIT when reading from / writing to IO ports

(You may as well want to take a look at the manual, like p.2-5 of the September 1975 Manual) During the execution of an IN or OUT instruction [..], how does the Intel 8080 react to its READY pin ...
Raffzahn's user avatar
  • 226k
4 votes

Did any big-iron systems implement offloaded database IO tasks?

It's not really clear what system you may have heared of, but for sure no mainframe. For one, use of conventional microprocessors for processing in mainframes type systems only started in the late ...
Raffzahn's user avatar
  • 226k
4 votes

Maximum speed of serial I/O bit-banged by 8-bit CPU

On the 6502, a lot depends upon the placement of the bits in whatever I/O register is being used or--for reception--if one bypasses the use of an I/O register entirely. The fastest reception from a ...
supercat's user avatar
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3 votes

Difference between the 8255 and 8042 PPIs

The 8255 is a PPI, the 8042 isn't, and neither is the 8288 a PPI but it is a Bus Controller which decodes the native 8088 CPU control bus signals into separate usable bus control signals to have ...
Justme's user avatar
  • 33.9k
3 votes

Are there multiple models of the Intel 8089 IOP?

[...] scheme of the last number being -2 on 8mhz versions -1 for 10mhz versions [...] They are not versions but speed grades. Versions are donated by letters after the base number. There is no fixed ...
Raffzahn's user avatar
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